JPS6120952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory scan device that sequentially reads out data from a memory in which data such as reception frequency and timer setting time are stored, and in particular, scan operation is performed quickly and data is read out quickly. I am trying to suggest something that can be done.

FIG. 1 is a system diagram of a conventional memory scan device of this type. Reference numeral 1 denotes a memory that stores data such as the reception frequency in a tuner of a stereo receiver or the set time of a timer provided in connection with this receiver, and is composed of RAM, ROM, MNOS transistors, and the like. When the read command signal from the write/read switching circuit 2 and the address signal from the address register 3 are supplied to the memory 1, the data stored in the memory 1, such as the reception frequency and timer setting time, are transferred to the data register 4. The contents are further supplied to a display device 5 consisting of an LED, a fluorescent display tube, etc., and the reception frequency, timer setting time, etc. are digitally displayed. A 3-bit address control signal of "000" to "111" is supplied from the counter 12 to the address register 3, and this is performed by the following operation. When the memory scan switch 6 as an operation switch is pressed, first, the voltage applied from the power supply 7 to both ends of the resistor 8 connected in parallel with this is supplied to the OR circuit 9, and the output of the OR circuit 9 is used as a reset signal for the counter. 12, the counter 12 is reset and its 3-bit output becomes "000". Next, the voltage obtained across the resistor 8 as the memory scan switch 6 is pressed is supplied to the set terminal of the R-S flip-flop circuit 13,
The output of the S flip-flop circuit 13 is supplied to a clock generation circuit 14, and the clock is supplied to a presettable counter 15. Note that the OR circuit 2 is set by pressing the memory scan switch 6 in advance.
0 is supplied with a specified voltage, and the presettable counter 15 is reset by its output. The presettable counter 15 is delayed by a predetermined delay amount, for example, 4 to 5 seconds, which is determined by the setting state of the external lead-out terminal 16. Supplied to the clock terminal. Based on this clock, a 3-bit address data signal is sequentially sent from the counter 12 to the address register 3, and an address signal is supplied from the address register 3 to the memory 1. On the other hand, when the memory scan switch 6 is pressed, a control signal for the write/read switching circuit 2 is supplied, and a read control signal is supplied from the write/read switching circuit 2 to the memory 1. Based on this operation, data such as the receiving frequency in the tuner of the stereo receiver, the timer setting time, etc. are supplied from the memory 1 to the display device 5 via the data register 4, and are sequentially displayed on the display device 5. Next, when the stop switch 17 is pressed, the voltage applied from the power supply 18 to both ends of the resistor 19 connected in parallel with it is supplied to the reset terminal of the R-S flip-flop circuit 13, and the R-S flip-flop circuit 13 is placed in the reset state. Therefore, the supply of the clock signal from the clock generation circuit 14 to the presettable counter 15 is stopped.
When the 3-bit output of the counter 12 becomes "111", a reset signal is supplied to the reset terminal of the counter 12 via the AND circuit 10 and the OR circuit 9, and the counter 12 is reset to the initial state of "000". be done. Also, when the count state of the presettable counter 15 is satisfied, a reset signal is supplied from its output terminal to the reset terminal of the presettable counter 15 via the OR circuit 20.
5 is reset and returns to the initial counting state.

By the way, in the conventional memory scan device described above, each time the memory scan switch 6 as an operation switch is pressed, the output of the counter 12 starts from "000", and the memory 1 starts scanning from the first address corresponding to "000". , so data stored near the first address in memory 1 is read out relatively quickly, but data stored near the last address is not read out quickly; Addresses that have been read out may be difficult to read, and unnecessary displays based on unnecessary scans may occur.
It had the disadvantage of wasting time.

In view of the above, the present invention proposes a memory scan device that has a simple circuit configuration, performs memory scan operations quickly and reliably, and quickly reads out data stored at various addresses in the memory. It is.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals. The memory scan device according to the present invention includes a memory 1, an address register 3 for controlling the address of the memory 1, an address counter 12 for controlling the address register 3, and a memory scan device for supplying a memory scan signal to the address counter 12. This memory scan signal generation circuit has a signal generation circuit {13, 14, 15,; 6, 23}, and this memory scan signal generation circuit is a single control that interrupts the memory scan signal of a predetermined period and shifts the address sequentially. A signal is supplied to the address counter 12.

First, the memory scan signal generation circuit will be explained. Reference numeral 21 denotes a single control signal generation circuit consisting of an operation switch 6, a power supply 7, and a resistor 8. When the memory scan switch 6 as an operation switch is pressed, the voltage obtained across the resistor 8 is a memory scan signal. as clock generation circuit 22
is supplied to The clock generation circuit 22 includes an R-S flip-flop circuit 13, a clock generator 14,
It consists of a presettable counter 15 and an OR circuit 20, and when a set signal as a memory scan signal is supplied to the set terminal of the R-S flip-flop circuit 13, the flip-flop circuit 13
The output of the clock generator 14 is supplied as a drive signal to the clock generator 14, and the clock generation signal is supplied from the clock generator 14 to the presettable counter 15.
The presettable counter 15 has an external lead-out terminal 16
The number of bases the counter operates as is arbitrarily determined by the following, and the clock signal is delayed by a predetermined amount of delay (for example, 4 to 5 seconds). By the way, prior to this counting operation, by pressing the operation switch 6, the specified voltage is set to the OR circuit 20.
The output is supplied to the reset terminal of the presettable counter 15, and the presettable counter 15 is set in the reset state. When the counting operation of the presettable counter 15 is completed, the output thereof is supplied to the reset terminal of the presettable counter 15 via the OR circuit 20, so that the presettable counter 15 is reset. The output voltage of the single control signal generation circuit 21 and the clock signal delayed by the presettable counter 15 are supplied to the OR circuit 23.
The output is sent to the counter 12 as a memory scan signal.
clock terminal.

As a result, the counter 12 performs a counting operation, and its 3-bit output is supplied to the address register 3 as an address control signal and also to the data register 25, and the data in the data register 25 is transmitted to the LED, fluorescent display tube, etc. A number (for example, 1 to 8) representing the memory area in which the reception frequency is stored in the memory 1 is digitally displayed on the display device 26. On the other hand, when the count function of the counter 12 is fulfilled and the 3-bit output becomes "111", a reset signal is supplied to the reset terminal of the counter 12 via the AND circuit 10, and the counter 12 is reset.
2 is in a reset state.

An address signal is supplied from the address register 3 to the memory 1 based on the address control signal from the counter 12, a read control signal is supplied from the write/read switching circuit 2 to the memory 1, and the stored contents of the memory 1 are transferred via the data register 4. The process of sequentially supplying the data to the display device 5 and displaying it on the display device 5 is the same as that shown in FIG. 1, so a redundant explanation thereof will be omitted.

By the way, if the operating switch 6 is pressed again during this memory scan operation, a signal is supplied to the clock terminal of the counter 12 via the OR circuit 23, so the counter 12 counts up, and each time the operating switch 6 is pressed. The data stored in the memory 1 can be quickly read out and the stored contents can be checked.

Next, in order to stop the change in the display of the data stored in the memory 1 on the display device 5 and maintain the display of the data at that time, by pressing the stop switch 17, the resistor 1
9 can be supplied to the reset terminal of the R-S flip-flop circuit 13 to put the R-S flip-flop circuit 13 into a reset state, and as a result, the clock generator 14 stops generating the clock. No clock provided;
The display of the data stored in the memory 1 on the display device 5 is maintained.

In this way, according to the memory scanning device of the present invention, scanning does not always start from the first address of the memory each time the operation switch is pressed, but if the operation switch is pressed sequentially, the memory is currently being scanned each time. Since the scan starts from the next address, the memory scan operation is performed quickly, and the data stored in the memory, such as reception frequency and timer setting time, is read out immediately regardless of the location of the stored address. Unnecessary scanning is not performed, and unnecessary displays and time wastage based on this will not occur.

In addition, in the above, the presettable counter 15
is provided simply to delay the clock signal, and can be replaced with a circuit having another delay function such as a monostable multivibrator.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a conventional memory scan device, and FIG. 2 is a circuit diagram of an example of the memory scan device of the present invention. 1 is a memory, 3 is an address register, 6 is an operation switch, 12 is a counter, 21 is a single control signal generation circuit, 22 is a clock generation circuit, and 23 is an OR circuit.

Claims (1)

[Claims] 1 comprising a memory, an address register for controlling an address of the memory, an address counter for controlling the address register, and a memory scan signal generation circuit for supplying a memory scan signal to the address counter, and for generating the memory scan signal. 2. A memory scan device according to claim 1, wherein the circuit supplies the address counter with a memory scan signal of a predetermined period and a single control signal that interrupts between the memory scan signals and sequentially shifts addresses.