JPS6123359A - Integrated cmos device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to semiconductor electronic devices, and in particular relates to three-dimensional CMOS devices [Prior Art] Complementary MO3 (CMOS) logic is one of the most popular applications in semiconductor technology. It is an important and well-known logic and has the advantage of low standby power consumption compared to other MOS type configurations.

However, these benefits can only be obtained at the expense of board area per logic unit.
For this reason, great efforts have been made to increase the degree of integration of CMOS devices, such as by creating devices in a stacked structure to save substrate area.

Recent polysilicon recrystallization technology using a laser beam enables stacked CMOS with a common gate.
It is now possible to manufacture

The basic method is to first deposit polysilicon on a quasi-n-channel device, recrystallize the polysilicon near and above the gate of the n-channel device using a laser beam, and then By doping the polysilicon afterwards,
p controlled by the same gate as the n-channel device
Form a channel device and
MO8 is obtained. Such a fabrication method is described, for example, by Collinzi et al.
1982) and Chen et al.
(IEEE Electron Device Le
'tters, pp. 272-274, 1983) contains a related description.

[Problem to be Solved by the Invention a] While the stacked structure type CMOS as described above has the inherent advantage of not causing latch-up development, it also has problems such as forming a gate oxide layer on a polysilicon layer. There are problems such as the manufacturing process is complicated and the structure is not planar.

As is well known, MOS transistors can be fabricated using Schottky barrier junctions at the source and drain. Such techniques have been applied to the fabrication of bulk CMO3 integrated circuits to prevent corrosion, but in this case p- and n-
Since both channel devices are formed within the bulk substrate, it is not possible to save on the substrate.For example, Sugino et al.
Rans-actions on Electron
Devices, pp. 110-118, 1!1183
(2013) contains related information. This Sugino Schottky barrier MOS device is manufactured by first forming a gate on an n-type silicon gate, and then forming a platinum silicide layer by performing platinum deposition and sintering.

[Objective of the Invention I Therefore, an object of the present invention is to save the substrate area, and to make it possible to manufacture a CMOS device with a simple structure and a simple manufacturing process.

[Means for Attempting to Solve the Problems] In a preferred embodiment of the method and device according to the present invention, p
A channel MOS device and an n-channel MOS device are merged together with the p-channel device on top of the n-channel device, and the source or drain region of the p-channel device serves as the gate for the n-channel device. Along with working,
The source or drain region of the n-channel device is configured to serve as a gate for the p-channel device. Both the p-channel and n-channel devices are non-self-aligned, and the p-channel devices are fabricated using, for example, polysilicon or bulk n-channel devices.

A source/drain contact between the silicide layers is provided as necessary. This p-channel device is a Schottky barrier source obtained by depositing titanium or other thermal metal material on a polysilicon layer followed by a sintering process to form a silicide layer as source and drain regions. It is also possible to configure it as a /drain MOS device.

Alternatively, the portion of the polysilicon layer that serves as the gate of the n-channel device is doped to form an n-type, and the −L plane of this n-type portion is silicided to bond it to the p+ polysilicon layer. It's okay.

Of course, the above combination of configurations may be merged with the n-channel device placed above the p-channel device. It is also possible to use an inversion induced conductivity type or an accumulation induced conductivity type, and it is also possible to use a non-silicon semiconductor material. Further, the combined CMOS device according to the present invention has a planar structure.

For upper devices, it is easily applicable to solid phase epitaxial growth. Yet again.

It is also possible to configure a CMOS latch by combining two such merged devices. Thus, the present invention enables the fabrication of a CMOS device with a simple structure and a simple manufacturing process, while saving the substrate area.

[Embodiment 1] In order to facilitate understanding of a preferred embodiment of the present invention, a standard 0MO5 U-Sochi will be described below with reference to the drawings. As shown in Figure 1.

A standard CMOS device basically consists of two n-channel devices 11.13 arranged in parallel,
Each has a p-channel device as a load. That is, on the large side, the p-channel device 15 serves as the load for the n-channel device 11, and the p-channel device 1 serves as the load for the n-channel device 13.
7 are provided respectively. The common drain of device 11.15 is coupled to the common gate of devices 13, 17, and likewise devices 13, 1? The common drains of are coupled to the common gates of devices 11.15, thus latching.

FIG. 2 separately shows the connection relationship between the p-channel device 15 and the n-channel device 13, - the p-channel device 17 and the n-channel device 1;
Needless to say, there is a similar connection between
In FIG. 2, gate 13 of p-channel device 15 is connected to drain 21 of n-channel device 13, and gate 23 of n-channel device 13 is connected to drain 25 of p-channel device 15.

The method and apparatus according to the present invention are intended to effectively exploit the advantages of a symmetrical connection configuration as described above.
Examples thereof will be described below.

Figure 3 shows the first method of manufacturing a CMOS device according to an uninvented method.
The preferred embodiment begins with forming a field oxide layer 37 on a p-type silicon veneer 31. (FIG. 3a) This p-type silicon substrate 31 is then patterned and implanted with arsenic to form the source and drain regions of the underlying n-channel device. In this case, it is assumed that the n-channel device is not self-aligned. The thus formed n-type source region is designated by 33, and the n-type drain region is designated by 35.
A gate oxide layer is grown on the silicon layer I-, as shown in FIGS. 3A and 3C, respectively.
In this case, the oxide layer is formed thicker on the n÷-type doped source region 33 and drain region 35 than on other parts, so that it has a reference numeral 38 on the substrate 311- and a reference numeral 41 on the drain region 35. Each is shown separately. A polysilicon layer 43 is then deposited on this oxide layer 313.41, followed by appropriate doping to obtain the desired properties. For example, a p-channel can be obtained by forming an inversion layer using a nyB impurity, a p-channel can be obtained by forming an accumulation layer using a p-type impurity, or an inversion layer or an accumulation layer can be obtained by using an intrinsic material. For example, a layer is formed. The p-channel is defined by a patterned oxide layer 45, as shown in FIG. polysilicon 4 in areas other than those protected by
After forming the silicide layer according to 3, the metal is removed to obtain the completed combined device as shown in FIG. 3e, where the silicide layer forming the source region of the upper p-channel device is removed. Code 4 for the part
7, a portion of the non-silicided polysilicon layer forming the p-channel region 45 is shown at 49, and a portion of the silicide layer forming the drain region is shown at 51, respectively. As is clear from this Figure 3e.

The drain region 51 of the two-part p-channel device forms the gate for the bottom n-channel device above the gate oxide layer 39, and the drain region 35 of the bottom n-channel device forms the gate for the top N-channel device below the gate oxide layer 41. Form the gate for the device.

Note that in the structure I-, neither the p-channel nor the n-channel devices are self-aligned, but the gate oxide layer is grown entirely on the bulk silicon substrate rather than on the polysilicon layer.

FIG. 3f shows an arrangement in which an opening 53 is provided in the oxide layer to symmetrically connect the upper p-channel device and the lower n-channel device on each side of the latch. Reference numeral 55 is an isolation field oxide layer.

FIG. 4 shows a second embodiment of the present invention, which differs from the embodiment described above in the formation process of the upper p-channel device. Firstly, as shown in FIG. 4a, the source and drain regions of this upper p-channel device may be doped rather than silicided, and in particular the polysilicon layer 43 (FIG. 3d) is formed on the substrate 31. Recrystallization may be performed by solid-phase epitaxy growth starting from the opening 53 where the interface with the crystal exists.The merged silicon structure of this example has a relatively planar shape, so that the epitaxial growth is difficult. It is particularly suitable for solid phase epitaxy growth since the growth does not need to proceed over vertical obstacles. After recrystallizing the polysilicon layer 43 as described above (this polysilicon layer 43 is
The recrystallization of step 3 may be carried out using a laser beam method), and further patterning of the oxide layer 45 and subsequent doping of the polysilicon layer 43 to form the p-channel region 49, as described above. P-type source and drain regions 47 and 49 are formed without silicidation as in the embodiment. however.

Finally, the resistance value may be lowered by partially siliciding these p-type source and drain regions. The structure thus obtained is shown in FIG. The silicide layer above .51 is indicated at 55.

FIG. 4 shows a modification of the embodiment described in FIG. 4a, in which an impurity region 52 is further provided on the large side. This impurity region 52 is doped to an n+ type, and in the structure shown in FIG.
It was part of the By changing to such an n◆ type doping, the region 52 becomes a gate for the lower n-channel device, thereby improving the operating characteristics of this n-channel device. Note that since the p-type drain region 51 is connected to the n-medium region 52 by the silicide layer 55, the regions 51 and 52
The flow of the electric wire is not stopped by the indirect contact or the table surface.The dimensions of the structure shown in FIG. 4 are typically as follows, for example. That is, the length of the p channel region 48 is 2 microns, the length of the p+ type drain region is 1 micron, the thickness of the oxide layer 45 is 1000 angstroms, the thickness X of the silicide layer 55 is 1000 angstroms, and the impurity-implanted polysilicon layer. Area 47.51.5
2 has a thickness of 3000 angstroms, gate oxide layer 41 has a thickness of 500 angstroms, gate a-oxide layer 39 has a thickness of 250 angstroms, and the length of n-channel region 40 directly below gate oxide layer 38 is 2 microns.
The thickness of the source region 33 and drain region 35 is 400 mm.
The thickness of the field oxide layer 37 can be 8,500 angstroms, and so on.

Referring now to FIG. 5, a method will now be described in which a pair of merging devices according to the preferred embodiment, such as a duplex, can be combined to simply and compactly construct a latch such as that shown in FIG. In FIG. 5, the pattern shown to the left of # represents the n+ diffusion layer forming the lower n-channel device, and the pattern shown to the right represents the titanium silicide layer forming the upper p-channel device. Each region of the pattern shown in FIG. 1 is given a reference numeral corresponding to each region of the device of FIG. Thus, the device 11 has a source region 61 and a drain region 83.

The device 13 consists of the source region 68, the drain region 21, and the gate 23 on the channel region 71, and the device 17 consists of the source region 73 and the drain region 75.
, a gate 77, and a p-channel region 78,
Device 15 consists of source region 81, drain region 25, gate 18, and p-channel region 83.
The connection between the drain regions of device 15.11 is made by a vertical connection 85 between the diffusion layer and the titanium silicide layer through the opening 53 in the oxide layer described above in connection with FIG. 3f; Similarly, the connection between the drain regions of devices 13 and 17 is made by a vertical connection 87. On the other hand, the cross-connection 88 between the drain regions of devices 11 and 15 and the gate of device 13.17 is partly through the vertical connection 85 and partly through the upper left quadrant of the left-hand pattern shown in FIG. Similarly, connected via a diffusion region,
Drain regions of devices 13 and 17 and device 11
．． A part of the connection 81 between the 15 goos 4 is a vertical connection part 87
and partly through the diffusion region in the upper right quadrant of the left pattern shown in FIG.

Although various uninvented embodiments have been described above, the method and apparatus according to the present invention are not limited to these embodiments.9 For example, the level of doping may be changed variously, and the n-channel device may be It may be placed above the channel device, the operation mode may be enhancement mode or depletion mode, and it may be of inversion induced conductivity type or accumulation induced conduction type.

It is also possible to use non-silicon based semiconductor materials.

[Effect of the Invention 1 As described above, the uninvented combined CMOS device includes a substrate having a first source and drain region and a first channel region between these regions, an insulating layer covering at least a portion of the first drain region; a second layer having a second source and drain region and a second channel region between these regions; Part of the second
the second channel region faces at least a portion of the first drain region and the second drain region faces at least a portion of the first channel region. a second layer is disposed, the first source, drain and channel region forming a first MOS device with the second drain region as the gate; A second MOS device is formed using the first drain region as a gate,
This has the effect of saving the substrate area and making it possible to manufacture a CMOS device with a simple structure and a simple manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a standard CMOS latch, FIG. 2 is a wiring diagram showing the connection relationship between the gate and drain in the CMOS latch shown in FIG. 4 is a cross-sectional view showing the second embodiment of the method according to the present invention, and FIG. 5 is a view showing an example in which a CMOS latch is constructed by combining CMOS according to the present invention. be. 31, p-type silicon substrate. 33. Source region of the lower an-channel device. 35, , drain i region of lower n-channel device (
)@gate of p-channel device). 3L 41. , ,gate oxide layer. 43...Polysilicon layer. 49, , p-channel region. 47, , Source region of upper Np channel device. 51, , the drain region of the upper p-channel device (
gate of the bottom n-channel device). Applicant Texas Instruments O Incorporated Ft'gJσ Ft'g, JC Fig, 3b Ft, JC Ft, 3d Ft'g, 3f F/'g, 4σ Ft'g, 4b Procedural amendment (method) l Case Indication Japanese Patent Application No. 60-90792 2 Name of the invention Merged CMOS device 3 Relationship to the case of the person making the amendment Patent applicant address 135004 North Central Expressway, Dallas, Texas, USA Agent address
150 Address 1-20-2-5 Dogenzaka, Shibuya-ku, Tokyo Date of amendment order July 10, 1985 (Shipped on July 30, 1985) 6 Number of inventions increased by amendment 07 Target of amendment Specification "Detailed Description of the Invention" column, "Brief Description of Drawings" column and Drawing (Plan) 7-1. The Detailed Description of the Invention column is amended as follows. (1) "Figure 3" on page 15, line 7 is corrected to [Figures 3a to 3f]. (2) Correct "Figure 4" in the first line of page 18 to "Figures 4a to 4b." 7-2. The column for the brief description of the drawings should be corrected as follows. (1) Page 24, item 6, “Figure 3” [Figure 3a, Figure 3b, Figure 3c, Figure 3d]
Figures 3e and 3f are corrected. (2) Correct "Figure 4" on the 6th line of page 24 to [Figures 4a and 4b].

Claims (16)

[Claims] (1) (a) a substrate having a first source and drain region and a first channel region between these regions; and (b) covering at least a portion of the first region and the first drain region. (c) a second layer having second source and drain regions and a second channel region between these regions, wherein at least a portion of the insulating layer is covered by the second layer; and the second channel region covers the first channel region.
opposite at least a portion of the drain region of the drain region and said second
(d) arranging the second layer so that a portion of the drain region faces the first channel region; a first MOS device formed by the second source, drain, and channel regions, and further formed by the second source, drain, and channel regions to form a second MOS device having the first drain region as a gate. device. (2) The combined CM according to claim 1, wherein (a) the first MOS device is an n-channel device, and (b) the second MOS device is a p-channel device.
OS device. (3) The combined CM according to claim 1, wherein (a) the first MOS device is a p-channel device, and (b) the second MOS device is an n-channel device.
OS device. (4) The combined CMOS device according to claim 1, wherein (a) the second layer is substantially planar. (5) The combined CMOS device according to claim 1, wherein (a) the second source and drain regions are formed of an impurity-implanted semiconductor material. (6) The combined CMOS device according to claim 5, further comprising (a) a silicide region interposed within the second source and drain regions. (7) (a) doping the second drain region to invert the conductivity type between the second channel region and a portion of the second drain region facing the first channel region; 7. The combined CMOS device according to claim 6, wherein a plurality of portions of the second drain region are bonded to each other by the silicide region by (b) introducing impurities of different conductivity types. (8) (a) The second source and drain regions are formed of silicide.
The combined CMOS device described in section. (9) The combined CMOS device according to claim 1, wherein (a) the second layer is formed of a material having characteristics resulting from solid phase epitaxial growth. (10) (a) a substrate having first source and drain regions and a first channel region between these regions; (b) covering at least a portion of the first region and the first drain region; (c) a second layer having second source and drain regions and a second channel region between these regions, wherein at least a portion of the insulating layer is covered by the second layer; and the second channel region covers the first channel region.
(d) the first source; a first M gated by the second source region by a drain and channel region;
1. A combined CMOS device comprising: an OS device; and a second MOS device using the first source region as a gate, formed by the second source, drain, and channel regions. (11) (a) having first source and drain regions and a first channel region between these regions;
(b) a substrate having second source and drain regions and a second channel region between these regions, and connecting the first and second source regions to a first power supply terminal; 1 and a second channel region and the first
and an insulating layer covering a portion of each of the second drain regions; (c) having a third source and drain region and a third channel region between these regions; and a fourth source and drain region. and a second layer having a fourth channel region between these regions and connecting the third and fourth source regions to a second power supply terminal, (d) of the insulating layer. at least a portion of the second layer, the third channel region faces at least a portion of the second drain region, and the fourth channel region faces at least a portion of the first drain region. and a portion of the fourth drain region faces the first channel region.
further coupling the first drain region to the third drain region and coupling the second drain region to the fourth drain region; (e) coupling the first drain region to the fourth drain region; , the drain and channel regions form a first MOS device with the fourth drain region as the gate, and the second source, drain and channel region form a first MOS device with the third drain region as the gate. forming a device and said third
The source, drain and channel regions form a first MOS device with the second drain region as the gate, and the fourth source, drain and channel region form a first MOS device with the first drain region as the gate. A combined CMOS latch characterized by forming two MOS devices. (12) (a) the first MOS device and the second MOS device are n-channel devices, and (b) the third MOS device and the fourth MOS device
12. The combined CMOS latch according to claim 11, wherein the S device is a p-channel device. (13) The combined CMOS latch according to claim 11, wherein (a) the second layer is substantially planar. (14) The combined CMOS latch according to claim 11, wherein (a) the third source and drain region and the fourth source and drain region are formed of an impurity-implanted semiconductor material. (15) (a) The combined CMOS latch according to claim 14, further comprising a silicide region interposed in the second and fourth source and drain regions. (16) (a) The third and fourth drain regions are doped so that the third and fourth drain regions are opposite to the second channel region and the first channel region, respectively.
and (b) bonding the plurality of portions of the third and fourth drain regions to each other through the silicide region by introducing impurities of different conductivity types. A combined CMOS latch according to claim 15 comprising: