JPS6138501B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-chip microcomputer having a read-only memory in which user-specified storage information (user program) is written, and in particular, the present invention relates to a one-chip microcomputer that has a read-only memory in which user-designated storage information (user program) is written. The present invention relates to a one-chip microcomputer that is capable of checking its operation to see if it exists.

Conventionally, the method for checking the user ROM (read-only memory) of a one-chip microcomputer, that is, the mask ROM that allows the storage information to be set arbitrarily according to the user's specifications, in a single one-chip microcomputer is to use a memory dump. There is a method that checks whether the program contents specified by the user have been written based on the function, or a method that uses a mounting tester to execute two ROM programs and compare and check their operations.

However, the former method simply checks whether the contents of the user program have been properly written, and does not check the operation of the user ROM by executing the program.
It is not possible to check whether the program is functionally correct. In addition, in the latter method, it is possible to check the operation by the user program by turning on the restore terminal and running the program. Due to the fact that
If the user program contains CALL instructions, JMP instructions, etc., even if the program in the user ROM is executed, the program loop of the above specific instructions will be executed repeatedly, making it difficult to check the entire program contents in the user ROM. There was a drawback that I couldn't do it.

The present invention solves the above problems,
Even if there is a program for a specific processing routine for a branch instruction such as a JMP instruction or a CALL instruction in the user ROM, it will be put into a no-operation state and the program written in the user ROM will be forced to start from address 0. An object of the present invention is to provide a one-chip microcomputer that can access up to the final address and check whether there are any functional defects in a user program.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a functional block diagram of a microcomputer according to the present invention, in which 1 is a read-only memory (hereinafter referred to as ROM) in which a user program is written, and 2 is a ROM 1 for user programs. and a central processing unit (hereinafter referred to as CPU) that controls and manages input/output devices, etc. (not shown) and executes calculations, transfer processing, etc. necessary to process a given task, and is
The CPU 2 specifies the address of the ROM 1, and the address counter 3, which is incremented every fetch cycle, and the address counter 3 and the ROM.
an address buffer 5 connected between the address buses 4 of the ROM 1; and a data buffer 8 connected between the external data bus 6 and the internal data bus 7 of the ROM 1.
is connected to the internal data bus 7, and is connected to the ROM1.
an instruction register 9 that temporarily stores the instruction code written from the instruction register 9; an instruction decoder 10 that decodes the instruction code stored in the instruction register 9; and a controller that generates control signals and timing signals necessary for executing the instruction. 11, an arithmetic logic unit (hereinafter referred to as ALU) 12 that executes arithmetic and logical operations, a general-purpose register 13, an accumulator 14, and a temporary register 1 that store data necessary for the operation.
The ALU 12, the general-purpose register 13, the accumulator 14, and the temporary register 15 are connected to the internal data bus 7, and the internal control unit 16 sent from the control unit 11 The signal bus 17 is designed to be supplied to the address counter 3, address buffer 5, data buffer 8, instruction register 9, instruction decoder 10 and arithmetic section 16.

FIG. 2 shows that when JMP instructions, CALL instructions, etc., which are the object of the present invention, are read, these instructions are invalidated and converted to no-operation instructions, and the contents of address counter 3 are incremented by 1 and the next instruction is executed. In other words, even if there is a JMP instruction, CALL instruction, etc. in the program, the corresponding subroutine program call,
Alternatively, it shows a specific example of a circuit means that can forcibly run a program in ROM 1 from address 0 to the final address without specifying a destination address. In FIG. 2, an instruction decoder 10 that decodes an 8-bit instruction code sent from an instruction register 9 has the following information:
A large number of instructions for sending to the control unit 11 instructions such as data transfer instructions, arithmetic and logic operation instructions, branch instructions (JMP, CALL, RET), I/O instructions, status specification instructions, NOP instructions (no operation instructions), etc. Output lines X ₁ , X ₂ , ...X _o are provided, among which the subroutine program is called.
Between the output line X ₂ for the CALL instruction and the output line X _i for the JMP instruction that specifies the destination address and ground, there is an element for disabling the instruction, such as a MOS transistor Q ₂ ,
Q _i is connected, and each transistor is turned on to the gate of this MOS transistor Q ₂ and Q _i .
Gate control circuit to turn off (inverter circuit)
18 is connected to the input terminal of the gate control circuit 18, and an input terminal 19 for disabling instructions is connected to the input terminal of the gate control circuit 18. A logic signal for enabling or disabling instructions by external operation is input to this input terminal 19. It is becoming more and more common. Further, the instruction decoder 1
0 NOP instruction output line X _o has 2 input OR gate 2
0 is connected, and the output signal from the gate control circuit 18 is input to the other input terminal of the OR gate 20.

Furthermore, the external data bus 6 includes a CPU.
A data memory (RAM) 21 for writing/reading data used in the program execution process, such as the data of the calculation result in step 2, and a status indicator 22 consisting of an LED, etc. for checking the program are connected via a status latch circuit 23. connected.

Next, the operation of the apparatus of the present invention configured as described above will be explained.

For a function check of the contents of a user program on the manufacturer's side without external equipment controlled by a computer, first, the instruction invalidation input terminal 19 is held at the logic signal "L" by an external operation. As a result _, the output of the gate control circuit 18 becomes "H _" as shown in FIG.
The CALL command output line _X2 and the JMP command output line _Xi are grounded and held so that the execution operations for the CALL and JMP commands are disabled.

Upon completion of initialization in this state,
When the CPU 2 is started, the contents of the address counter 3 are transferred to the address buffer 5 and the address bus 4.
It is sent to the user program ROM1 via. As a result, the address of the ROM 1 is specified starting from address 0, and the instruction stored at that address is temporarily stored in the instruction register 9 through the data buses 6 and 7. The command stored in the command register 9 is decoded by the command decoder 10, it is determined what kind of operation the command performs, and a command signal is sent to the control unit 11 based on the determination. The control unit 11 sends control signals and timing signals to the calculation unit 16, address counter 3, instruction register 9, instruction decoder 10, etc. in response to the instruction to execute the instruction operation. The status information associated with the execution of this command operation is sent to the status latch circuit 23 via the external data bus 6, where it is decoded according to the definition of the status information, and the output is used to operate the status indicator 22 to check the program. I do.

Furthermore, when a fetch cycle including instruction reading and instruction decoding is completed by the address counter 3, the address counter 3 is incremented each time, and based on the contents, the program instruction in the ROM 1 stored at the next address is reading,
The instruction operation will be executed from address 0 of ROM1 to the final address.

On the other hand, the address in ROM1 where the CALL instruction or JMP instruction, etc. is stored is the address counter 3.
When specified by , these instructions are taken into the instruction register 9 through the data buses 6 and 7 as in the normal case, and at the same time are decoded by the instruction decoder 10, and the decoded signal of the CALL instruction or JMP instruction is Each output line X ₂ or X _i
Sent from At this time, these output lines
Since X ₂ and X _i are grounded by MOS transistors Q ₂ and Q _i , they are sent to the output lines X ₂ and X _i
The decoded signals of the CALL and JMP commands flow to the ground through the respective MOS transistors Q ₂ and Q _i and do not issue any instructions to the control section 11 . Therefore, the instruction operations of the arithmetic unit 16 and the like by the CALL instruction and the JMP instruction are not executed. Also, at this time, since the logic signal "H" from the gate control circuit 18 is applied to the control unit 11 as a NOP command via the OR gate 20, the control unit 11 that has received the command does not do anything to the calculation unit 16, etc. The contents of address counter 3 are simply changed without giving an operation command.
1 to specify the ROM address of the next address where the CALL instruction, JMP instruction, etc. is stored.

After the manufacturer side has completed checking the program contents of ROM1 as described above, when the program is actually executed by connecting an external device on the user side, "H" level logic is input to the instruction invalidation input terminal 19 by external operation. Add the signal. In this way, the output of the gate control circuit 18 is always held at "L", and
Since the MOS transistors Q ₂ and Q _i connected to the output lines X ₂ and X _i of the CALL and JMP instructions are kept in the OFF state, the CALL and JMP instructions are not invalidated.

As described above, according to the present invention, the program
The output line of the instruction decoder that decodes the instructions read from the ROM is
A circuit means for disabling the JMP instruction is provided, so that when the manufacturer checks the program contents, the JMP and CALL instructions are disabled, resulting in no operation, and the address counter of the ROM is increased by 1. Program the ROM
Since it is forcibly run from address 0 to the final address regardless of JMP or CALL instructions, CALL and CALL instructions are
Even if the JMP instruction exists, this prevents some programs from being repeatedly executed. Therefore, the program written in the ROM can be executed completely from address 0 to the final address, and the user can
This has the advantage of being able to reliably check whether there are any functional defects in the program.

[Brief explanation of the drawing]

FIG. 1 is a functional configuration diagram of a one-chip microcomputer according to the present invention, and FIG. 2 is a circuit diagram showing an example of a circuit for invalidating the JMP instruction, etc. according to the present invention. 1...ROM, 2...CPU, 3...Address counter, 9...Instruction register, 10...Instruction decoder, 11...Control unit, 16...Arithmetic unit, 18...
...Gate control circuit section, 19...Input terminal for command invalidation, 21...Data memory, 22...Status indicator.

Claims (1)

[Claims] 1: a read-only memory that stores at least a user program; an address counter that specifies an address for the read-only memory; an instruction decoder that decodes a program instruction read by addressing the address counter; and instructions for the instruction decoder. A microcomputer comprising: a control unit that sends out control signals and timing signals for executing command operations; and an arithmetic unit that executes command operations in response to each command based on the control signals and timing signals from the control unit, The output side of the instruction decoder is programmed.
A circuit means for disabling the execution of branch instructions such as JMP and CALL instructions is provided, and the circuit means ignores the branch instruction and forcibly runs the program in the read-only memory from address 0 to the final address. A one-chip microcomputer characterized by the following features: