JPS6143744B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a virtual computer system implemented in a computer system having a virtual storage system, and particularly to an address translation device thereof.

A virtual memory method is a virtual address that is determined separately from the address (real address) that indicates the location of the data on the main memory when a processing device accesses data stored in the main memory. refers to the method of access.

The virtual storage method has been adopted in many computer systems in recent years, and its details are well known, so further explanation will be omitted.

Note that the correspondence between virtual addresses and real addresses is generally defined by an address translation table managed by software. Further, converting a virtual address to a real address is referred to as address conversion.

A virtual computer is a real computer that is used for time sharing.
Virtual hardware information (control registers, calculation registers, PSW, etc.) in each time slot
By setting up real hardware, one real computer operates as if it were a separate computer for each time slot. Therefore, a single computer can run multiple different operating systems at the same time.

Since the virtual computer method has recently been implemented in several computer systems, a more detailed explanation is not necessary.

In virtual machine systems, virtual storage is generally implemented in a multi-level configuration. Since this is the basic background of the present invention, it will be explained below.

Each virtual machine has a virtual address and a corresponding real address in order to access data on the main memory.
A real address for a virtual machine cannot directly become a real address on the main storage device.

This is because the main storage must appear to each virtual machine as if it were exclusively owned. Therefore, the real address for each virtual computer is a virtual address for the real computer, which is converted once again to become a real address on the main storage device.

As described above, in the virtual memory system of the virtual computer system, there are the following three levels of addresses.

(1) Level 1: Real address on main storage (real address for the real computer) (2) Level 2: Virtual address for the real computer (real address for the virtual computer) (3) Level 3: Virtual addresses for virtual machines The most basic three-level addresses are shown above, but in general, any number of intermediate level addresses can be set between level 1 and level 3. is clear. Therefore, although the present invention can be applied to a general virtual storage system with multi-stage addresses as will be described later, a specific explanation will be given regarding the three-stage case described above.

By the way, in a virtual memory system having three levels of addresses, the following two types of address translation tables are required.

(1) First address translation table……Level 3
Conversion from address to level 2 address (2) Second address conversion table……Level 2
Conversion from Address to Level 1 Address In general, in a virtual memory system having (M+1) levels of addresses, M types of address conversion tables are required.

However, conventionally, when actually accessing data in main memory using a virtual address, the hardware of a processing device cannot directly refer to the above address conversion table.

This is because conventional processing device hardware is designed without being aware of the virtual computer system, so a new address obtained by one address conversion is used as a real address. For this reason, in virtual computer systems, the shadow table described below has conventionally been prepared on the main memory under the responsibility of software and provided for reference by the processing device hardware.

That is, from the contents of the first and second address conversion tables, a correspondence table (shadow table) of level 1 addresses for all level 3 addresses is created in advance, and this table is referred to as the first and second address conversion tables. It is stored separately as data on the main memory. When accessing general main memory, you can obtain the real address through one address conversion by referring to the shadow table instead of referring to the first and second address conversion tables. This is possible.

FIG. 1 conceptually shows the relationship between address translation tables for addresses at each level.

A computer system using a virtual memory method generally has an address translation buffer inside the processing unit. This is an associative memory device that stores multiple pairs of virtual addresses and their corresponding real addresses.
It is called TLB (Translation Lookaside Buffer). The address translation buffer is a well-known technology and does not require any explanation.

When a virtual computer system is realized, the address translation buffer will store level 3 addresses and corresponding level 1 addresses. When accessing the main memory, if the desired address translation pair is not in the address translation buffer, the desired level 1 address is obtained by referring to the shadow table, and the level 1 address obtained and the original level 3 Register the address along with the address translation buffer.

Above, an outline of the conventional technology that implements a virtual memory method in a virtual computer system has been described.

Next, problems with such conventional technology will be explained. The shadow table is convenient in that there is no need to be aware that the hardware of the processing device is a virtual computer system, but this has some disadvantages in terms of performance.

The first point is that it takes a lot of time to generate a shadow table. One virtual space may have thousands to tens of thousands of pages, which are the minimum unit of address translation. Referring to the first and second address translation tables for each of them and creating a shadow table will require an average of 10 program steps per page. Therefore, to generate a set of shadow tables, a program with tens of thousands to hundreds of thousands of steps must be run.

The second point is that when it becomes necessary to update the information in the address translation table by swapping pages in main memory, not only the first or second address translation table but also the shadow table must be updated. Must not be. In reality, when it is difficult to partially update a shadow table, the entire shadow table relating to that space may be invalidated. In this case, if the space is to be accessed again later, the shadow table must be generated again, taking a long time as described above.

The third point is that the shadow table itself requires a very large storage capacity.

When thousands to tens of thousands of pages exist in one space, a storage area of at least tens of thousands of bytes is required as a shadow table. Since the shadow table, by its nature, must be resident in the main memory, the shadow table occupies a considerable portion of the main memory.

As mentioned above, the shadow table realizes a virtual storage system in a virtual computer system using conventional processing unit hardware.
It has the drawback that its generation and maintenance consumes a large amount of program running time and main storage area.

Moreover, although there may be a large amount of data in a set of shadow tables that is never used, program time and main storage space are consumed equally by these items. Time and resources for these are wasted.

An object of the present invention is to eliminate the need for the existence of a shadow table, which has the above-mentioned difficulties, by adding new functions to the hardware of a processing device, thereby increasing the program running time and the effectiveness of the main memory area. It is something.

The gist of the present invention is to enable hardware of a processing device to directly refer to the first and second address translation tables.

The content of the present invention will be explained below using an embodiment shown in FIG.

FIG. 2 is a block diagram showing part of a processing apparatus in which the present invention is implemented.

In FIG. 2, a virtual address for the processing device to access the main memory 14 is given to the signal line 1. This is input to address conversion buffer 2 and converted into a real address. To be more specific, a plurality of sets of virtual addresses are stored in the portion 20 of the address conversion buffer 2, and a plurality of sets of corresponding real addresses are stored in the portion 21, and one set is selected by a portion of the virtual addresses on the signal line 1. Output. The virtual address output from the address conversion buffer part 20 is compared with the virtual address 1 in the comparator 3, and if they match, the corresponding real address is set as the desired real address and accessed to the main memory via the gate 4 and the selector 10. It is applied to address line 11. If the results of the comparison in the comparator 3 do not match, the table reference control circuit 5 is activated in order to refer to the address conversion table in the main memory and obtain a desired real address.

When the table reference control circuit 5 is activated, it first refers to the first address translation table.

The register 60 stores the first address of the first address conversion table, and the contents of the register 60 are input to the adder 9 via the selector 7. Also, a part of the virtual address on the signal line 1 is input to the other side of the adder 9, and the result of this addition is used as the first address conversion table address on the line 11.
The main memory 14 is read out.

The contents of the first address conversion table read from the main memory 14 are level 2 addresses. These are set in the read data register 13 via the read data line 12 from the main memory 14.

Next, the control circuit 5 reads the second address conversion table. The register 61 stores the first address of the second address conversion table, and is input to the adder 9 via the selector 7. The other input of the adder 9 is a register 13.
A portion of the level 2 address set in 2 is input, and the result of addition is applied to the main memory access address line 11 via the selector 10 as a second address conversion table address.

The desired real address is written in the second address conversion table read from the main memory 14. This is read out via the main memory read data line 12 and set in the data register 13.
From there it is written to part 21 of address translation buffer 2 via signal line 14.

At the same time, the virtual address given to signal line 1 is also transferred to portion 20 of address translation buffer 2.
will be written to.

Through the above operations, the desired address translation pair was registered in the address translation buffer 2, and the virtual address for the processing device to access the main memory was able to be translated into a real address. The desired real address may be obtained by referring to the address translation buffer once again, or may be output from the register 13 to the signal line 11 via 8, 9, and 10.

That is, according to the present invention, a desired real address can be obtained by referring to an address translation table in the main memory, without requiring a shadow table whose creation and maintenance consumes a lot of time and resources. It is now possible to register it in the address translation buffer.

In the above embodiment, it is assumed that both the first and second address conversion table start addresses are stored in registers inside the processing device, but these may be stored as data in the main memory, for example. It's okay. In that case, register 60,
Instead of outputting 61 data, the necessary main memory access is performed.

In the above embodiment, in order to simplify the explanation, address translation from a level 3 address to a level 2 address and address translation from a level 2 address to a level 1 address are each performed by one set of address translation tables. However, the effectiveness of the present invention is clear even if this is based on a two-level (generally multiple-level) table such as a segment table and a page table, as seen in many prior art techniques.

Furthermore, the present invention can be easily extended as follows. That is, as mentioned earlier, the multiplicity of virtual addresses is not limited to the three levels shown in the embodiment, but may also be greater or lesser. Generally, when there are (M+1) virtual addresses, there are M sets of address translation tables. Therefore, in this case, the present invention can be implemented by providing M registers (or data areas on the main memory) indicating the start address of the address conversion table.

Furthermore, if the multiplicity of virtual addresses is made variable instead of being fixed on the hardware, the flexibility of the processing device can be increased and the performance can be improved.

The following methods can be considered for this purpose.

One method is to notify the processing device of the virtual address multiplicity M in the form of data in the register 62 or main memory inside the processing device.

At this time, the processing device reads M, refers to M sets of address conversion tables, and uses the result of referencing the Mth group of address conversion tables as a real address. However, in this method, if the first address of the address conversion table is stored as a register group inside the processing device, there is a restriction that M must be less than or equal to the total number of registers N.

The second method is to provide additional information for each register or data in which the start address of the address conversion table is written, and set therein information that specifies the order of address conversion. In this case, the order itself is fixed by the register position or the data position on main memory, and only the first address conversion, the last address conversion, or both are made variable. There is also.

As described above, the present invention makes it possible to perform address translation without the need to create and maintain a shadow table in a virtual memory system in which virtual addresses generally have a multiple structure. A large amount of time and resource consumption associated with maintenance could be eliminated.

The present invention has the disadvantage that the time required for one address translation (total time required for translation from the highest virtual address to the real address) is longer than when a shadow table is provided.

However, if the capacity of the address translation buffer is increased beyond a certain level, the probability of address translation occurring by referring to the address translation table can be sufficiently reduced, so the overhead for this can be reduced in terms of overall program processing time. The overhead associated with creating and managing the dow table is much smaller, and processing capacity can be improved.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram illustrating a virtual storage system having a double address translation table and a shadow table, and FIG. 2 is a block diagram illustrating an embodiment of the present invention. 2...Address conversion buffer, 3...Comparator,
4...Gate, 5...Table reference control circuit, 6
0 and 61...Registers that hold the start address of the address conversion table, 7, 8, and 10...
...Selector, 9...Adder, 14...Main memory.

Claims (1)

[Scope of Claims] 1. In a virtual computer system implemented in a computer system having virtual memory, M sets of address conversion means include a first address conversion means that converts a virtual address of a virtual machine into a second address. The K-th address converting means converts the K-th address into a (K+1)-th address, and the M-th address converting means converts the M-th address into a real address of the main memory device. a conversion means (where K=1, 2, . . . M-1), and an address translation buffer that holds an address translation pair indicating a virtual address of the virtual machine and a corresponding real address of the main storage device; and an indicator indicating the current address translation multiplex number M of the processing unit, and the processing unit attempts to convert a virtual address of the virtual machine to a corresponding real address of the main storage device using the address translation buffer. At this time, if the required address translation pair does not exist in the address translation buffer, the address translation means of the number of stages indicated by the indicator among the M stages of address translation means convert the required real address. An address translation device characterized in that the real address is obtained and registered in the address translation buffer together with the corresponding virtual address.