JPS6143909B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a solid-state imaging device with particularly enhanced application functions.

As an example of a conventional solid-state imaging device, FIG. 1 shows a schematic plan view of a one-dimensional solid-state imaging device equipped with a charge-coupled signal readout register. In FIG. 1, 1 is a plurality of photoelectric conversion elements that receive optical signals, generate signal charges, and is responsible for storage, and 2 is a channel for electrically and spatially separating each of the plurality of photoelectric conversion elements. 3 is a transfer gate for transferring the signal charge stored in the photoelectric conversion element 1 to the readout register; 4 is a signal for sequentially transferring the signal charge flux that flows in by opening the transfer gate 3 to the output section; A read register, in this case using a well-known charge-coupled device. That is, each signal charge flux photoelectrically converted by the photoelectric conversion element 1 and integrated over a certain period of time is transferred to each bit of the readout register 4 along the arrow 5 by opening the transfer gate 3, and in this case, charge coupling is performed. It is read out as an electrical output that is transferred sequentially along arrow 6 by normal operation of the device. In order to explain the conventional example shown in FIG. 1 in more detail, FIG. 2 shows a cross-sectional structural diagram taken along the line -. In this conventional example, a Pn junction photodiode is used as a photoelectric conversion element, 8 is an n-type impurity layer forming the main part of the photoelectric conversion element, and 9 is a semiconductor substrate of a solid-state imaging device. A P-type impurity layer forms a photoelectric conversion element together with an N-type impurity layer 8; 10 is a channel stop region made of a high concentration of P-type impurity that provides a barrier potential that defines the active region of the device; 11 is a channel stop region 3 in FIG. 12 is a corresponding transfer gate electrode, 12 is an n-type impurity layer forming a built-in channel of the charge-coupled device, 13 is a charge transfer electrode of the charge-coupled device, and 14 is a light shield that prevents light from leaking to areas other than the photoelectric conversion element. Each represents a membrane.
Now, a broken line 15 shows the potential distribution in the bulk along the cross section of the figure when the signal charge is integrated for a certain period of time with the transfer gate 11 closed. Shaded area 1
6 means the presence of a signal charge, and a solid line 17 represents a potential changed due to the presence of the signal charge. Next, when a positive voltage is applied to the transfer gate 11 in this state, the potential barrier is lowered as shown by the broken line 18, and the signal charge is transferred to the channel 12 of the charge-coupled device along the arrow 20.
leaks into The movement of the signal charges at this time is shown by a solid line 19, and when the amount of charges reaches the potential defined by the broken line 18, all the signal charges are transferred to the channel 12 of the charge-coupled device forming the signal readout register. Since the signal has been transferred, the transfer gate is closed again and the next signal charge integration operation is performed. On the other hand, the signal charge flux transferred to the readout register (FIG. 1, 4) must be completely read out before the next signal charge integration operation is completed. That is, the signal charge integration time Ti must be longer than the signal charge readout time. In addition, the signal charge readout time Tr
is often limited by the output signal processing circuit, etc., and a minimum readout time is set. Therefore, the minimum signal integration time Ti ^min is determined, which sets the upper limit of the incident light intensity. Conventionally, in order to increase the dynamic range with respect to the amount of light, many attempts have been made to provide a capacitive charge storage section, such as a MOS type, adjacent to a photoelectric conversion section. However, even with this method, strong incident light
In order to transfer all the charge flux Qsig generated during Ti ^min to the readout register, a large register capacity is required, which not only increases the area occupied on the semiconductor substrate. This increases the burden on the drive circuit that supplies drive pulses to each transfer electrode such as a charge-coupled device that forms a readout register.
This imposes a new lower bound on readout time. On the other hand, if the light-shielding film 14 shown in FIG. 2 is expanded to cover part of the photoelectric conversion elements 8 and 9, the effective photosensitivity will decrease and the amount of charge generated within the integration time Ti will be reduced. Decrease. However, in this case, S/N degradation such as an increase in the relative value of the dark current component due to a decrease in sensitivity is noticeable in the case of low incident light, and conversely, the dynamic range for incident light is reduced due to the usage limit for low incident light. It becomes a thing. Therefore, in the conventional solid-state imaging device, a limit on the amount of incident light (a dynamic range for the amount of incident light) is set by a limit on the signal readout time and the size (capacity) of the readout register.

The present invention provides a solid-state imaging device with a new structure that overcomes the above-mentioned drawbacks of conventional solid-state imaging devices, and by providing one or more divided electrodes in the photoelectric conversion region, it can respond to incident light. The present invention relates to a structure that expands the dynamic range for the amount of incident light by reading out only signal charges divided into appropriate amounts without increasing the size of the readout register.

The details of the present invention will be explained below with reference to an embodiment shown in FIGS. 3 and 4. FIG. 3 is a schematic plan view of a one-dimensional solid-state imaging device according to the present invention.
1, 22, 23, 24, and 25 each form a photoelectric conversion element, a shaded area 26 is a channel stop area for separating each photoelectric conversion element array in which the photoelectric conversion elements 21 to 25 are connected, and 27 is a channel stop area. A transfer gate 28 is a signal readout register for transferring part or all of the signal charge flux photoelectrically converted by the photoelectric conversion elements 21 to 25 to a readout register 28, and in this case, a charge coupled device is used. , the signal charge flux flowing in by opening the transfer gate 27 is sequentially transferred to the signal output section by the well-known operation of the charge-coupled device.

Signal dividing gates 29, 30, 31, and 32 provide the main structure of the present invention, and are preferably formed of transparent electrodes, forming a MOS structure over each photoelectric conversion element row. 33 is a sweep gate for flowing out the remainder of the divided signal charge flux to the drain 34, and can also serve as a blooming prevention gate. 34 is a drain for sucking out extra or unnecessary signals. That is, a series of photoelectric conversion element rows 21 to 25 form one photoelectric conversion region, and the next photoelectric conversion region is arranged with the channel stops 26 in between. Now, in order to explain the features of the present invention in detail, attention will be paid to one photoelectric region made up of a series of photoelectric conversion element arrays shown in FIG. 3, and a cross-sectional structural diagram taken along the line - is shown in FIG.

Numerals 36, 37, 38, 39, and 40 are n-type impurity layers, which together with the P-type semiconductor substrate 41 form a Pn junction type photoelectric conversion element array. 42 is a transfer gate electrode for transferring part or all of the signal charge flux generated and integrated in the photoelectric conversion region to a readout register; 43 is a charge coupled device used as a readout register in this embodiment; 44 is an embedded channel of the read register, 45, 46, 47, 48 are dividing gates that are a feature of the present invention, and 49 is a part of the transfer electrode other than the read signal divided by the dividing gate. A sweep gate for flushing out unnecessary charges to the drain, 5
0 is a drain for sucking out unnecessary charges flushed out by opening the sweep gate, and is formed of a highly concentrated n-type impurity layer. 51
is a positive voltage power supply in this case applied to the drain 50; 53 is an insulating layer such as SiO ₂ ; 54 is a light-shielding film to prevent light from leaking to areas other than the photoelectric conversion region; Each is represented. The features of the present invention will be explained below using actual driving examples. Now, considering the signal integration period, the transfer gate 42 is in the OFF state (zero potential in this case), and the dividing gates 45, 46, 4
7 and 48 are in the ON state (positive voltage applied), the sweep gate 49 is in the OFF state (zero potential or slightly positive potential), and the potential distribution is as shown in the broken lines 55 and 58 and the solid line 58 by the signal charge 57 in FIG. is shown. If the signal charge amount Qi generated within the constant integration time Ti is smaller than the transferable charge amount Qr per stage of the readout register, the division gates 45 to 48 remain in the ON state, and the transfer gate 42 is turned ON (positive voltage applied). All signal charges generated by this state are transferred to a read register (44 in FIG. 4) and then sequentially transferred to be output. On the other hand, for example, if Qi is in the range of 5/4Qr<Qi<5/3Qr, the divided electrode 47 is set to OFF state (approximately zero potential) after the integration time Ti, and the signal charge becomes 3:3 as shown in FIG. 5b. 2, the barrier potential under the divided electrode 60
(However, it is assumed that the simple dividing gates are arranged at equal intervals). After that, turn on the transfer gate 42 and sweep gate 49.
By setting the state, 3/5Qi (hatched area 61) is transferred to the readout register as a readout signal charge and read out, and 2/5Qi (hatched area 62 is transferred to the drain 66 by turning on the sweep gate 49). This condition is shown in Figure 5c, where arrows 63 and 64 indicate the direction of signal charge transfer to the drain and signal readout register, and 65 indicates the buried channel of the charge coupled device used as the readout register. This shows the signal charges that have moved to the area (44 in Figure 4).In this way, only the signal charges that have been divided at an appropriate division ratio are read out in the register according to the amount of signal charges generated by the amount of incident light within a certain period of time. In this example, in order to simplify the explanation, a structure in which four dividing gates are arranged at equal intervals is taken up, but it is not necessary that the division gates are arranged at equal intervals. As will be described later, it is often more practical to have a structure in which the distance from the transfer gate 42 increases.In the embodiment of FIG. 4, by closing the dividing gate 48 (OFF state), the total integration 4/5 of the charge, by closing the dividing gate 47, 3/5 by closing the dividing gate 46, 2/5, by closing the dividing gate 45
1/5 will be used as read charge.
On the other hand, as shown in Fig. 3, the photoelectric conversion areas separated from each other by channel stop areas are connected in the vertical direction of the paper of Fig. 4, but the signal division ratio is constant across all photoelectric conversion areas. is clear, and there is almost no decrease in the S/N ratio due to division. The division ratio in this case is often determined by the amount of charge that can be transferred per stage of a readout register such as a charge-coupled device, as shown in the operation example of FIG. FIG. 6 shows the relationship between the readout signal amount and the product of the element surface illuminance and the integration time (hereinafter referred to as lux·sec product) in the above embodiment. The horizontal axis of the figure is lux・
Sec product, the vertical axis represents the readout signal charge amount. 67
68 is the dividing gate 48 in FIG. 4, and 69 is the dividing gate 47, 70 when all the dividing gates are open.
The dividing gates 46 and 71 represent the readout signal charge amount - lux when the dividing gates 45 are closed and divided.
sec product, and 74 represents the maximum amount of charge Qr that can be transferred per one stage of the read register. In other words, as the amount of light increases, the amount of signal charge increases,
By closing the splitting gate with a smaller splitting ratio at the point when Qr is crossed, 67 → 68 → 69 → 70
→ Can be used by switching to 71. This driving method will be described in more detail with regard to a second embodiment which is a somewhat modified version of the first embodiment of the present invention shown in FIG. The characteristic diagram shown in Fig. 7 shows that the dividing ratio of dividing gates 45 to 48 in Fig. 4, that is, the interval between each gate, is changed at a ratio of 1/5: 1/4: 1/3: 1/2: 1. It shows the relationship between the readout signal charge amount and the lux·sec product when a structure that expands as it goes away from the gate 42 is applied, and the horizontal axis is the lux·sec product.
The vertical axis of the sec product indicates the readout signal charge amount. 77 is the reading when all the division gates are open, 78 is when the division is divided into 1/2, 79 is when it is divided into 1/3, 80 is when it is divided into 1/4, and 81 is when it is divided into 1/5. Each represents the amount of signal charge. 82 indicates the maximum amount of charge Qr that can be transferred per one stage of the read register. Here, if the signal integration time is Ti, the element surface illuminance is Lx, the photoelectric conversion coefficient is η, and the area of the photoelectric conversion region is Ae, the total signal charge amount Qi is given by Qi=η·AeLx·Ti. Now, Lx is very small and 0<Qi<
In the state of Qr, that is, LxTi<Qrη·Ae, that is, the area 83 in FIG. 7, the transfer gate is opened with all the division gates open and the signal is read out. The amount of light increases and Qr＜Qi＜2Qr, that is, Qr／η・Ae
If <LxTi<2Qr/η・Ae, it corresponds to region 84, the first division gate (1/2 division) is closed, the signal amount is divided into 1/2, and the read signal Qs is Qs=
Let 1/2・Qi (<Qr). Similarly, 2Qr/
In the case of η・Ae<LxTi<3Qr/η・Ae, that is, in the region 85, it is divided into Qs=1/3Qi (<Qr), and in the case of 3Qr/η・Ae<LxTi<4Qr/ηAe, that is, in the region 86, Qs=1 Divide into /4Qi (<Qr),
4Qr/η·Ae<LxTi<5Qr/η·Ae, that is, in the region 87, it can be divided into Qs=1/5Qi (<Qr) and read. This means that by applying the present invention using the same readout register, in this embodiment, a dynamic range of light amount five times greater than that of the conventional solid-state imaging device was obtained. By applying the present invention, a dynamic range for N times the amount of light can be obtained by generally dividing the light by a minimum of 1/N. The advantages of applying the present invention are not limited to this. For example, in conventional solid-state imaging devices, attempts have been made to provide additional capacitance in the photoelectric conversion region or to reduce the sensitivity in order to increase the dynamic range with respect to the amount of light. On the other hand, a dark current component is a factor that degrades the S/N ratio of a solid-state imaging device. Now, if the generation rate of dark current is ξ, and the equivalent area of the added capacitance for dark current is Ai, then the amount of noise charge Qd due to dark current is Qd = ξTi (Ae +
Ai). Also, if the sensitivity attenuation coefficient, such as attenuating the incident light, is ξ, the signal charge amount is Qi
= εηAeLxTi. Therefore, the S/N ratio of the signal to the dark current is Qi/Qd=εηLxAe/ξ
(Ae+Ai). Therefore, in the conventional solid-state imaging device, when ε is small or when Ai is large, the S/N ratio decreases. However, when the present invention is applied, Ai is not necessarily required (it may be provided), and ε is 1, and Qi/Qd=η
It becomes Lx/ξ. Therefore, if the signal component Qi becomes 1/N, the dark current component Qd also becomes 1/N, so that no deterioration of the S/N ratio occurs.

Next, another embodiment of the present invention is shown in FIG. 8th
In the figure, 88 is a first photoelectric conversion element, 89 is a second photoelectric conversion element, 90 is a 1/2 division gate that divides the photoelectric conversion elements 88 and 89 into equal areas, 91 is a first transfer gate, 92 is a second transfer gate, 9
3 is a channel stop region separating each of the photoelectric conversion regions constituted by the first and second photoelectric conversion elements 88 and 89; 94 is a first readout shift register; and 95 is a second readout shift register. represent Now, considering the integration period of the signal charge,
The 1/2 division gate 90 is open (ON state), and the pair of photoelectric conversion elements 88 and 89 are electrically fully conductive, so that the same amount of charge is accumulated. Naturally, in this state, the transfer gates 91 and 92 are closed. After a certain integration time, the 1/2 dividing gate 90 closes (zero potential), so that completely equal amounts of signal charges are divided into 88 and 89 and stored. Thereafter, by opening the first and second transfer gates 91 and 92, the divided signal charges are transferred to the first and second readout registers 94 and 95, respectively, along arrows 96 and 97. Ru.

With the above operation, both read registers 94, 9
5, there are exactly the same signal sequences. The existence of such equal signal charge trains provides significant advantages with respect to output signal processing. For example, when considering the case where these signal strings are to be binarized, the signal string moved to the first readout register 94 is first read out, the maximum value and average value of the output are detected, the optimal slice level is set, and the appropriate slice level is set. Later, the second signal charge train transferred to and stored in the second readout register 95 can be read out and binarized optimized by the slice level. 100 in FIG. 9 indicates an output signal, and a chain line 101 indicates an example of a slice level.

As described above, by applying the present invention, it is possible to increase the dynamic range with respect to the amount of incident light without increasing the capacity of the readout register, and not only does it not deteriorate the S/N ratio. As a result, the chip area of the solid-state imaging device can be reduced. Furthermore, as explained in the other embodiments, operations suitable for signal processing can also be made possible. Note that implementing the present invention does not result in any increase in the manufacturing process. In other words, the split note, which is a feature of the present invention, can be manufactured in the same process as the polycrystalline silicon or Al transfer electrode, which is essential when manufacturing ordinary charge-coupled devices. , transparent electrodes made of polycrystalline silicon give better results. Note that all of the above embodiments refer only to the case where a pn junction photodiode is used as the photoelectric conversion element, but the present invention naturally includes the following:
This is also possible with MOS type photoelectric conversion elements. However, in that case, it is more effective for the MOS type divided gates to be arranged in close proximity or in an overlapping gate structure.

[Brief explanation of the drawing]

FIG. 1 is a plan configuration diagram of a conventional solid-state imaging device.
FIG. 2 is a cross-sectional structural diagram taken along the line - of FIG. 1, FIG. 3 is a plan configuration diagram of a one-dimensional solid-state imaging device according to the present invention, and FIG. 4 is a cross-sectional view of the present invention taken along the line - of FIG. Fig. 5 is a potential distribution diagram for explaining the principle of dividing charge carriers by split electrodes, Fig. 5 a shows the structure when all the photoelectric conversion parts are in a conductive state, and b shows the voltage distribution under the split electrodes. When a signal charge carrier is divided by forming a potential barrier at FIG. 7 is a characteristic diagram of the amount of readout signal charge versus the amount of incident light according to the first embodiment of the present invention, FIG. 7 is a characteristic diagram of the amount of readout signal charge versus the amount of incident light in a modification of the first embodiment, and FIG. FIG. 9 is a plan view of another embodiment of the present invention, and FIG. 9 is a diagram showing a read signal processing method for one application example of the embodiment of FIG. 21, 22, 23, 24, 25... Divided photoelectric conversion element, 26... Channel stop region, 2
7...Transfer gate, 28...Read register, 28,
29, 30, 31, 32...divided gate electrode, 33
... Sweeping gate electrode, 34... Sweeping drain, 3
6, 37, 38, 39, 40...n-type impurity layer, 4
1... P-type impurity semiconductor, 42... Transfer gate electrode,
43...Transfer gate electrode, 45, 46, 47, 48
...Divided gate electrode, 49...Sweeping gate electrode, 5
0... Sweep drain, 88, 89... Equally divided elements of photoelectric conversion region, 90... Equally divided gate electrode, 91, 92... Transfer gate electrode, 93... Channel stop region, 94, 95... Read register.

Claims (1)

[Claims] 1. A plurality of photoelectric conversion elements formed on a substrate and generating charge carriers according to the amount of incident light; comprising a divided electrode formed, a transfer gate for transferring charge carriers generated by the plurality of photoelectric conversion elements, and a transfer means for transferring the charge carriers transferred by the transfer gate to an output section, A solid-state imaging device characterized in that the amount of charge carriers transferred to the transfer means can be controlled by adjusting the voltage applied to the electrodes. 2. In the solid-state imaging device according to claim 1, the photoelectric conversion element is formed of a pn junction type photodiode, and the divided electrode includes an insulating layer formed on the surface of the photodiode. A solid-state imaging device, characterized in that it is partially formed through a. 3. The solid-state imaging device according to claim 2, wherein a transparent electrode is used as the divided electrode. 4. In the solid-state imaging device according to claim 1, the photoelectric conversion element has a MOS type structure in which a plurality of transparent electrodes are formed on the surface of the substrate with an insulating layer interposed therebetween, and each electrode A solid-state imaging device characterized in that the structures are arranged close to each other or overlapped with each other, and have functions of accumulating and dividing charge carriers at the same time. 5. In the solid-state imaging device according to claim 1, a readout electrode takes out one of the charge carriers divided by the dividing electrode as a signal, and a drain absorbs and removes the other charge carrier;
A solid-state imaging device comprising an electrode for separating or electrically connecting the drain and the photoelectric conversion element. 6. In the solid-state imaging device according to claim 1, two charge carrier columns divided by the same division ratio in all the photoelectric conversion elements by the division electrodes are each independently converted into a time series signal. A solid-state imaging device characterized by comprising a means for taking out the image.