JPS6154253B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semiconductor integrated circuit, in particular, using polycrystalline silicon as element electrodes, inter-element wiring, or both, and selectively oxidizing active regions and field regions using a silicon nitride film. The present invention relates to a method for manufacturing integrated circuits in a self-aligned manner using a method, and particularly provides a manufacturing method for easily realizing a structure that can solve problems that arise when miniaturization is performed. Hereinafter, as an aid to clarifying the effectiveness of the present invention, the conventionally known silicon gate field effect transistor (hereinafter referred to as silicon gate MOSFET) will be described.
We will take up semiconductor integrated circuits that include
First, we will explain the structural defects that are highlighted when miniaturization occurs. In FIG. 1a, a p-type impurity diffusion layer 12 and a thick field oxide film 13 are formed as a channel stopper in the field region of a p-type silicon substrate 11 having a resistivity of several Ω·cm by selective oxidation, and the active region and Gate insulating film 1 on the silicon substrate surface to be formed
4 and a polycrystalline silicon gate electrode 15G.
After forming the inter-element wiring 15C, an active region not covered by the polycrystalline silicon gate electrode 15G (a region represented by an intra-element wiring region is added to the element region represented by the source, gate, and drain). A high concentration of n-type impurity is doped into the semiconductor substrate (region involved in carrier phenomenon) by diffusion or the like to form a source region 16 and a drain region 16 which also function as internal wiring regions. 1 is a schematic cross-sectional view showing the basic structure of a semiconductor integrated circuit including a gate MOSFET. In addition, although the p-type is illustrated as the first conductivity type and the n-type is illustrated as the second conductivity type, these are only examples. The above-mentioned problems when miniaturizing a semiconductor integrated circuit that includes a silicon gate MOSFET as a functional element and polycrystalline silicon as an inter-element wiring are the layer resistance of the polycrystalline silicon part and the n-type diffusion layer that becomes the source or drain. The layer resistance becomes very high. The main reason for this is that in order to miniaturize a silicon gate MOFET without impairing its electrical characteristics, it is necessary to scale down the dimensions not only in the two-dimensional direction of the semiconductor surface but also in the three-dimensional direction, that is, in the depth direction. This is because it has to be reduced. For example, the width of the gate polycrystalline silicon of the commonly used silicon gate MOSFET is 5.
~6μm, source/drain junction depth 1.5~
On the other hand, in the case of short channel silicon gate MOSFETs which are currently in the development stage, the gate polycrystalline silicon width is about 2 μm or less. Along with this, the n-type diffusion layer junction depth in both the source and drain regions has also become very shallow, 0.5 μm or less. When making particularly shallow junctions like this, it is not possible to make the impurity concentration of the n-type layer sufficiently high, so the layer resistance becomes several tens of Ω/□ or more. The layer resistance of the polycrystalline silicon introduced also ranges from several tens of Ω/□ to 100
In some cases, it reaches Ω/□. In addition, the thickness of polycrystalline silicon does not directly affect the electrical characteristics of the silicon gate MOSFET, so it is not necessary to follow the scale-down rule, but the narrower the width of polycrystalline silicon, the more In reality, the film thickness must be reduced in order to maintain the processing accuracy and to reduce the probability of disconnection at subsequent steps such as metal wiring, which is also one of the causes of increased layer resistance. Figure 1b shows a perspective partial cross-sectional view of a conventional large-scale integrated circuit that uses polycrystalline silicon and n-type impurity diffusion layers with high layer resistance as inter-element wiring, intra-element wiring, etc. To further clarify the point. As is clear from FIG. 1b, the internal wiring using the n-type impurity diffusion layer 16 from the power supply point F from the high-order metal wiring to the electrode portion E1 or E2 of the field effect transistor ignores the resistance of each part. In this case, they are connected to the same power feeding point F in terms of the circuit. However, in reality, the resistance of these parts cannot be ignored as the scale of the integrated circuit increases, and it is difficult to place the elements and feed points at equal distances due to various constraints, which causes various problems. This will occur. In particular, the n-type impurity diffusion layer 1 reaching the electrode E1
The internal wiring of E2 is longer than that of E2, and an unnecessary high-resistance component is present, and the voltage drop there becomes impossible to ignore. For example, if the power supply point F is at ground potential, there is a risk that the actual ground potential will rise; conversely, if the power supply point F is at the power supply potential, there is a risk that the actual power supply voltage will drop; This will significantly reduce the operating margin of the integrated circuit.
Similarly, polycrystalline silicon 15C with high layer resistance
When used as inter-element wiring in an electrical signal transmission circuit, the signal propagation delay time increases, which becomes a major obstacle to increasing the speed of integrated circuits. Therefore, a structure has been proposed that can eliminate the drawbacks of the conventional structure described above, especially the drawbacks when miniaturized. That is, as shown in the perspective partial sectional view in FIG.
The n-type impurity diffusion layer 16, which has a shallow junction depth as shown in FIGS. By newly providing an impurity diffusion layer 18 which functions exclusively as an internal wiring of the element, it is possible to reduce the resistance of the internal wiring of the element, which could not be achieved with the shallow impurity layer 16 shown in FIGS. By effectively solving the problem and leaving the impurity layer 17 having a conventional shallow junction depth in the device electrode component where a shallow junction depth must be maintained in accordance with the scale-down rule, The aim is to realize the desired large-scale integrated circuit. However, when attempting to actually manufacture the new structure proposed by this proposal, for example, FIG. 2, a new problem arose. Most of these problems can be said to be problems in manufacturing technology, but they became a major barrier when implemented on an industrial scale. The details will be described later with a detailed explanation of the present invention, but to give an example, 1. there are problems such as wire breakage and a decrease in yield due to the large step difference in the laminated structure; 2.
3. This makes miniaturization difficult because the polycrystalline silicon layer must be formed thickly.
The disadvantages include a large number of steps, etc. It is an object of the present invention to eliminate these drawbacks of conventional methods and to ensure that the new structure proposed above can be manufactured easily. The manufacturing method according to the present invention has the following features. That is, a first silicon nitride film is formed on the surface of the first conductivity type semiconductor substrate in areas other than regions to be used as inter-element isolation regions, a channel stopper and a field oxide film are formed using this first silicon nitride film as a mask, and then The first silicon nitride of a partial region of the first silicon nitride film, that is, a region that will become a future device region, including a region that will become a source and a drain by forming a second conductivity type impurity layer with a shallow junction depth. After removing the film, a thin insulating film that will become a gate insulating film in the future is formed on the entire surface of this removed region, and a polycrystalline silicon layer is further placed on the region that will become a gate electrode in the future and the region that will become inter-device wiring. The second silicon nitride film, the polycrystalline silicon layer, and the remaining portion of the first silicon nitride film are used as a mask to pass through the exposed thin insulating layer and form the second silicon nitride film. An impurity exhibiting a conductivity type is shallowly introduced into the surface layer of the first conductivity type substrate to form a second conductivity type impurity layer having a shallow junction depth with the source and drain, and then the exposed thin insulating film and the exposed A silicon oxide film is formed on the surface layer of the polycrystalline silicon layer, the remaining first silicon nitride film and second silicon nitride film are removed, and impurities exhibiting the second conductivity type are sufficiently introduced from this removed region. , a second conductivity type impurity layer having a deep junction depth connected to the second conductivity type impurity layer having a shallow junction depth is formed on the first conductivity type semiconductor substrate in the first silicon nitride film region to achieve low resistance. This method of manufacturing a semiconductor integrated circuit is characterized in that the polycrystalline silicon layer in the second silicon nitride film region is also used as a low resistance inter-device wiring of a second conductivity type. Hereinafter, a conventional manufacturing method of a semiconductor integrated circuit having an impurity diffusion layer 17 which becomes a device electrode with a shallow junction depth and an impurity diffusion layer 18 which becomes an internal wiring of a device with a deep junction depth connected to the impurity diffusion layer 17 shown in FIG. 2 will be described below. about,
The main steps will be described based on FIG. 3, which schematically shows the steps, and the problems caused by the steps will also be described. FIG. 3a shows a p + layer 22 as a channel stopper and a thick field oxide film 23 formed by selective oxidation using a silicon nitride film 24 patterned and formed on a p ^- type silicon substrate 21 with a resistivity of Ωcm as a mask. It shows the formed state. In FIG. 3b, the silicon nitride film 24 on the active region used as a selective oxidation mask is completely removed, a gate insulating film 25 is deposited on the removed region, and then a layer of 5000 to 6000 Å thick is added to the surface of the gate insulating film 25. A fairly thick polycrystalline silicon film 26 is shown deposited by the usual CVD method. Figure 3c shows a width of about 2 μm that will become the gate electrode in the future.
Leaving the striped polycrystalline silicon film 26G and the polycrystalline silicon film 26C that will become inter-device wiring, cover the parts that will become the source formation region S , drain formation region D , and active region A that will become the internal wiring in the future. After removing the existing polycrystalline silicon film using a normal photolithography method, a device electrode is formed over the entire active region through the thin insulating film 25 using the polycrystalline silicon 26G that will become the gate electrode and the field oxide film 23 as a mask. The figure shows a state in which an n-type impurity layer 27 having a shallow junction depth is introduced by, for example, ion implantation, and at the same time, n-type impurities are also introduced into a gate electrode 26G and a polycrystalline silicon 26C that will become an inter-element wiring. Figure 3d shows that during thermal diffusion to form an n-type diffusion layer with a deep junction depth, which will later become the internal wiring of the device, the n-type impurity layer 27 with a shallow junction depth, which will become the device electrode, is not affected at all. A silicon oxide film 28 with a thickness of 2,000 to 3,000 Å is applied to the surfaces of the polycrystalline silicon 26G, 26C and the active regions A ,
It shows the state in which it was deposited on the surfaces of S and D using a thermal oxidation method. During this thermal oxidation, if the thin insulating film 25 in the active regions A, S, and D is a silicon oxide film, it is not necessary to forcefully remove it. However, since the surface and side surfaces of the polycrystalline silicon are oxidized and consumed by this thermal oxidation, it is necessary to allow for a thickness reduction of 1000 to 1500 Å from the beginning when depositing the polycrystalline silicon. Furthermore, the surface of the impurity layer 27, which is provided in the active region and has a shallow junction depth, will naturally be consumed by oxidation, and the interface between 28 and 27 will become deeper than it was originally, so of course it is necessary to anticipate a corresponding change from the beginning. . In addition, when ion-implanting the n-type impurity layer 27 with a shallow junction depth into the polycrystalline silicon 26G and 26C that will serve as gate electrodes or inter-element wiring, a low concentration of n-type impurity is simultaneously implanted, resulting in a slightly lower resistance. However, it still exhibits a very large layer resistance value of several tens of Ω/□. Therefore, it is necessary to form the polycrystalline silicon sufficiently thick from the beginning so that the resistance is still sufficiently low. On the other hand, however, if the thickness of polycrystalline silicon is increased too much, it becomes difficult to control the patterning process to achieve fine dimensions due to overetching of the side surfaces, leading to problems in processing accuracy. Furthermore, since the level difference becomes very large, there is also the disadvantage that the probability of disconnection of high-order metal wiring, etc. increases. Due to the above-mentioned circumstances, when using the above-mentioned conventional manufacturing method, it is not possible to find an appropriate value for the thickness of polycrystalline silicon that solves all the problems. The present invention aims to eliminate this drawback and provide a manufacturing method that can obtain a low layer resistance value with thin polycrystalline silicon. FIG. 3e shows that a sufficiently high concentration n-type impurity layer 29 is formed by removing the silicon oxide film 28 covering the region A where the n-type impurity layer 29 with a deep junction depth, which will become the internal wiring of the device, is to be provided. Later, silicon oxide film 2
At least A to insulate the A area from which 8 has been removed.
A state in which a new insulating film 30 is formed in the region is shown. This new insulating film 30 is usually deposited by a thermal oxidation method after high concentration impurity diffusion.
It has already been eaten away when attaching the silicon oxide film 28 for protection of shallow junctions, and will be eaten away again from the lower position. Therefore, when it is formed in this way, the interface between the insulating film 30 and the impurity layer 29 is initially It is located one step deeper than the position of the gate oxide film. As a result, the surface irregularities become extremely large, which not only increases the probability of disconnection of high-order metal wiring, but also increases the probability of disconnection in the high-order metal wiring.
9 sinks deeply, the contact area with the channel stopper 22 increases, resulting in disadvantages such as an increase in junction capacitance. Hereinafter, the main steps of a typical embodiment of the present invention will be explained with reference to FIG. 4. In FIG. 4a, a silicon nitride film 34 is patterned and formed as a mask on a p-type silicon substrate 31 with a resistivity of Ωcm, and a p ⁺ layer 32 and a thick field oxide film 33 are formed as a channel stopper by selective oxidation. The figure shows the state in which it has been formed. In the conventional method, at this point, the silicon nitride film 34 on the active region used for selective oxidation is completely removed and a gate insulating film is deposited.However, in the present invention, as shown in FIG. Leaving the silicon nitride film 34 covering the surface of the active region where an n-type impurity diffusion layer with a deep junction depth and low resistance is to be formed, both the source and drain regions with a shallow junction depth (Fig. 4d) are left in place. , e, f 38).
After removing the silicon nitride film on the surface of the active region where a MOSFET is to be formed, a silicon oxide film 35 of about 400 Å is formed on that part.
Furthermore, a polycrystalline silicon film 36 with a thickness of about 4000 Å and a silicon nitride film 37 are further deposited on the surface by, for example, the usual CVD method. Figure 4c shows a width of about 2 μm that will become the gate electrode in the future.
Leaving the striped polycrystalline silicon film 36G and the polycrystalline silicon film 36C serving as inter-element wiring, other source formation regions S and drain formation regions D and impurity diffusion layers with low resistance and deep junction depth are formed. This shows the state where the polycrystalline silicon film in region A has been removed using silicon nitride films 37G and 37C as an etching mask. Figure 4d shows an n
The type impurity diffusion region 38 is formed by a silicon nitride film 34,
37G and polycrystalline silicon 36 which becomes the gate electrode
This shows a state formed using ion implantation or the like using G as a mask. FIG. 4e shows the side surfaces of the polycrystalline silicon 36G, 36C and the shallow junction depth source region S and drain region D using the second silicon nitride film 37 as a mask.
This shows the state in which oxide films 39G and 39C are deposited on the surfaces of by thermal oxidation. This oxide film 39G needs to have a sufficient thickness to protect the shallow junction 38 when forming an impurity diffusion layer with a deep junction depth later.
The interface between 9G and 38 is located at a much deeper position than before thermal oxidation. Note that silicon nitride films 34 and 37
Since G and 37C are hardly oxidized, 34 and 31
The interface between the two does not move at all. FIG. 4f shows silicon nitride films 34 and 37.
G and 37C are removed, and a low resistance, deep junction depth n-type diffusion layer 40 is formed in the region A , which is connected to the shallow junction depth n-type diffusion layer 38 of the S and D regions, and is to be formed in the device wiring. is formed by thermal diffusion method etc.,
At the same time, the n-type impurity is sufficiently diffused into the polycrystalline silicon 36G that will become the gate electrode and the polycrystalline silicon 36C that will become the inter-element wiring, and the surface of the diffusion layer 40 and the polycrystalline silicon 36 at the deep junction depth are newly added.
It shows a state in which an insulating film 41 is deposited on the surface of G, 36C by thermal oxidation method or the like. At this time, since the n-type impurity diffusion region 38 having a shallow microstructure is protected by the silicon oxide film 39G covering its surface, the n-type impurity is not diffused and a shallow junction depth can be maintained. Furthermore, since the thermal diffusion of the deep junction depth n-type diffusion layer 40 is performed at the time the silicon nitride film 34 is removed, there is no penetration into the depth of the silicon surface during the previous oxidation. Surface irregularities are reduced, and the probability of disconnection of high-order metal wiring is also reduced. In this way, according to the present invention, an element with a fine structure having an impurity region with a sufficiently shallow junction depth, a diffusion layer serving as a wiring having a deep junction with a sufficiently low layer resistance, and a polycrystalline silicon with a low layer resistance. High-performance semiconductor integrated circuits can be manufactured easily and with high precision. The manufacturing method of the present invention is characterized by a device electrode consisting of a second conductivity type impurity layer with a shallow junction depth provided in the device region and a second conductivity type impurity layer connected to the second conductivity type impurity layer with a deep junction depth provided in the active region. The purpose of the present invention is to separate the formation of the internal wiring region consisting of the device wiring region by leaving a part of the first silicon nitride film already used in the selective oxidation of the field region. Furthermore, a second silicon nitride film having approximately the same thickness as the first silicon nitride film used in the selective oxidation method is formed so as to cover the polycrystalline silicon that will form the gate electrode and inter-device wiring. The surfaces of the regions not covered with the first and second silicon nitride films and the field oxide film and the side surfaces of the polycrystalline silicon are covered with a somewhat thick oxide film, and then the second conductivity type impurity having the shallow junction depth is formed. It is applied to the polycrystalline silicon and the internal wiring area in the active region with a deep junction depth, that is, the surface portion exposed when the overlying silicon nitride film is removed, without affecting the layers. The purpose is to diffuse sufficient impurities at the same time. Therefore, according to the present invention, in a semiconductor integrated circuit using polycrystalline silicon as an element electrode, an inter-element wiring, or both, a low resistance polycrystalline silicon wiring and a low resistance Forming internal wiring within a device without affecting the high-performance, fine device electrodes made of a second conductivity type impurity layer with a shallow junction depth, and with the ease of partially modifying the conventional manufacturing method. As a result, the performance of the integrated circuit can be significantly improved. In the present invention, since polycrystalline silicon is etched using a silicon nitride film as a mask, in the process immediately before adding impurities to form a deep junction, for example, when forming an oxide film covering the surface of a shallow junction element electrode, polycrystalline silicon is etched. Since there is no reduction in thickness, there is no need to make the polycrystalline silicon thicker in anticipation of the reduction in thickness, and it can be made thinner from the beginning, which has the advantage of improving etching accuracy and reducing steps. In addition, since the surface of an impurity layer with a shallow junction depth will be covered with an oxide film of an appropriate thickness, the impurity layer with a deep junction depth and polycrystalline silicon should be doped with a sufficiently high concentration of impurity. This method can be carried out without affecting the impurity layer having a shallow junction depth at all, and has the advantage that the impurity layer having the deep junction depth and polycrystalline silicon can be prepared to have a very low layer resistance value. For example, 0.3μm
If we consider the case where arsenic ions are implanted to obtain shallow source and drain junctions, the layer resistance in the relevant region is usually on the order of several tens of Ω/□. The layer resistance of a thick layer of polycrystalline silicon is also as high as several tens of Ω/□, and it is not uncommon for it to exceed 100 Ω/□.
However, according to the present invention, the impurity layer with high layer resistance and shallow junction depth formed in the element region remains in an extremely narrow region that serves as the source or drain, and the active region, which serves as other internal wiring, has a deep junction depth. Because it can be formed with 10Ω/□ or less, the layer resistance can be kept at an extremely low layer resistance of 10Ω/□ or less, and the resistance of polycrystalline silicon can also be easily lowered to a low layer resistance of about 10Ω/□ to 20Ω/□. has advantages.

[Brief explanation of the drawing]

FIG. 1a is a partial cross-sectional view schematically showing the basic configuration of a semiconductor integrated circuit that uses miniaturized polycrystalline silicon as element electrodes or inter-element interconnections with the conventional structure. b is a perspective partial cross-sectional view including the surrounding area. FIG. 2 is a perspective part for explaining an improved structure that was proposed prior to the present invention to solve the drawbacks of the conventional structure shown in FIGS. 1a and 1b, and is basically the object of the present invention. FIG. Figure 3 a, b, c, d,
In order to explain the conventional manufacturing method that has been adopted to realize the improved structure whose basic structure is shown in FIG. Figure 4 a, b, c, d, e, f
1 schematically and conceptually shows the main steps of a typical example of the manufacturing method improved by the present invention. Each symbol in the figure indicates the following. S :
A region constituting a source in the element region,
D : A region in the element region that forms the drain, A : A region in the active region that forms an impurity layer with a deep junction depth that forms the interconnection within the element, E1 : and E2 : Regions that constitute device electrodes, such as the source and drain of field effect transistors,
F : Feeding point connecting higher-order metal wiring and internal wiring,
G: Subscript meaning gate, C: Subscript meaning inter-element wiring, 11, 21, 31: First conductivity type semiconductor substrate, 12, 22, 32: Field doping region forming channel stopper, 13, 23,
33: Field oxide film, 14, 25, 35: Thin insulating film, 15, 26, 36: Polycrystalline silicon,
16: A conventional second conductivity type impurity layer with a shallow junction depth that serves both as an element electrode and an internal wiring at the same junction depth, 17: A shallow junction for element electrodes based on an improved proposal Second conductivity type impurity layer with a deep junction depth, 18: A second conductivity type impurity layer with a deep junction depth dedicated for internal wiring according to an improvement proposal, 2
4: silicon nitride film, 27: second conductivity type impurity layer 17 with shallow junction depth formed by conventional manufacturing method, 28: silicon oxide film, 29: deep junction depth formed by conventional manufacturing method Second conductivity type impurity layer 18, 30: an insulating film formed continuously to 28 to cover the surface of the active region A , 3
4: First silicon nitride film, 37: Second silicon nitride film newly formed by the method of the present invention, 38: Shallow junction depth formed by the method of the present invention. Second conductivity type impurity layer 17, 3
9: Silicon oxide film newly formed by the method of the present invention; 40: Second conductivity type impurity layer 18 with a deep junction depth formed by the method of the present invention.

Claims (1)

[Claims] 1. A first silicon nitride film is formed on the surface of the first conductivity type semiconductor substrate in areas other than regions to be formed as inter-element isolation regions, and a channel stopper and a field oxide film are formed using this first silicon nitride film as a mask. The first silicon nitride film in a region that will become a future device region, including a partial region of the first silicon nitride film, that is, a region to be formed as a source and a drain by forming a second conductivity type impurity layer with a shallow junction depth. After removing this, a thin insulating film that will become a gate insulating film in the future is formed on the entire surface of this removed area,
Furthermore, a polycrystalline silicon layer is patterned and formed in a region that will become a gate electrode in the future and a region that will be an inter-device wiring, together with a second silicon nitride film to be placed thereon, and this second silicon nitride film and polycrystalline silicon layer are formed. Using the silicon layer and the remaining portion of the first silicon nitride film as a mask, an impurity exhibiting a second conductivity type is shallowly introduced into the surface layer of the first conductivity type substrate through the exposed thin insulating film to form the source and drain. A second conductivity type impurity layer with a shallow junction depth is formed, and then a silicon oxide film is formed on the exposed thin insulating film and the exposed surface layer of the polycrystalline silicon layer, and the remaining first silicon nitride film and Second
The silicon nitride film of the silicon nitride film is removed, and impurities exhibiting the second conductivity type are sufficiently introduced into the removed region.
A second conductivity type impurity layer having a deep junction depth connected to the second conductivity type impurity layer having a shallow junction depth is formed on the first conductivity type semiconductor substrate in the silicon nitride film region, thereby forming a low resistance inter-element wiring. A method for manufacturing a semiconductor integrated circuit, characterized in that a polycrystalline silicon layer in the second silicon nitride film region is also used as a second conductivity type low-resistance inter-element wiring.