JPS6167326A - Am receiver - Google Patents

Abstract

PURPOSE:To reduce gain suppression due to a disturbing wave, by dividing the level control of an intermediate frequency (IF) level into two stages and making the level control of the front stage by means of an IF envelope detecting output and that of the rear stage by means of a synchronism detecting output. CONSTITUTION:The output of an IF amplifier 5 is envelope-detected by a level detector 6 and the gain of the IF amplifier 5 is controlled with the output of the detector 6, and then, the output of the IF amplifier 5 is inputted in another IF amplifier 10. At a synchronism detector 7, AM synchronism detection is performed by multiplying the output of the amplifier 10 by a signal synchronous to the carrier of an IF signal obtained by means of a PLL circuit 8. The level of the IF signal is fixed by controlling the gain of the amplifier 10 by using the DC component of the synchronism-detected 7 signal passing through a LPF11 and the output of the detector 7 is outputted as an audio signal through another LPF9. In this case, the output of the amplifier 10 is maintained at a fixed level since the output of the LPF11 is proportional to the amplitude of the received input signal, and thus, the influence of a disturbing wave can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an AM receiver, and in particular to an AM synchronous detection system.
Regarding the M receiver.

BACKGROUND ART Conventionally, this type of AM receiver has a configuration as shown in FIG. In the figure, the signal is applied to the microphone f2 via an antenna-powered URF (high frequency) amplifier 1, and mixed with the oscillation signal of the local oscillator 3. This mixed output nBPF (
An IF (intermediate frequency) signal is extracted by a bandpass filter 4 and input to an IF amplifier 5.

The IF amplifier 5 has a gain-controllable configuration, and the output of the IF amplifier 5 is supplied to a level detector 6 for envelope detection, and the gain of the IF amplifier 5 is controlled according to this level detection output. It has become.

Then, in the IF small output synchronous detector 7 of the IF amplifier 5, AM synchronous detection is performed by multiplying the IF defect signal carrier obtained by the PLL (phase locked loop) circuit 8 with a signal synchronized with the IF signal carrier. This detection output is derived as an audio signal via an LPF (low pass filter) 9.

With this configuration, the fl and PLL circuits 8 are locked in and the IF
Since it takes a certain amount of time to obtain a signal synchronized with the flaw signal carrier, if an excessive input is applied to the IF amplifier 5 etc. during this time, it is necessary to detect and prevent this excessive input. In order to suppress the gain of the IF amplifier 5 during this period, a level detector 6 is used to apply so-called AGC.

Here, the angular frequency of the engineering F signal is ω. Binding, BPF
4 center frequency ω. If there is an interference wave angular frequency (ω.+Δω) in the output obtained by passing through the
ω) t=A(t+(B/A)2+2(B/A)oos
dωt)1'2- ooe(w.t + ψ(t))
・-・-(1)tp(t)xp taa-' ((B/
, ()ainj ωt l/ [1+ (”/A)Go
” 0) t l−<t+. When this is level detected by the detector 6, A (1+ (B/A) 2+ 2
(M'4 God lω1) A DC component called Vz is extracted. Therefore, if B\0, the DC component (t)Do of this level detection output will be higher than the signal component level A. This f(t) DC controls the gain of IF Ang 5, but the level of the interference wave is B=
If it is 0, the f(t) Do null level detection output will accurately detect the level of the received signal and will not cause the same problem.

However, if interference waves occur and B\0, the level of the level detection output f(t) DC will be higher than the actual received signal level A, so B = 0 without interference waves.
The audio output will be smaller than in the case of
Since tlDo similarly changes, a problem arises in that even if the received signal level A is constant, the audio output level changes.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones described above, and its purpose is to control the gain of another IF amplifier based on the DC level of the synchronous detection output, thereby eliminating interference. An object of the present invention is to provide an AM receiver that reduces gain suppression caused by waves.

The AM receiver according to the present invention is configured to detect the output level of the IF amplifier, control the gain of the IF amplifier according to the detected output, and synchronously detect the AM signal using the gain-controlled IF ratio output. The present invention is aimed at an AM receiver, and its feature lies in that it is configured to further control the level of the gain-controlled IF flaw signal in accordance with the output from the synchronous detection.

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals.

In the figure, another second IF amplifier 10 is provided between the IF amplifier 5 and the synchronous detector 7, and like the IF amplifier 5, this is a gain control type amplifier. As the gain control signal for this IF amplifier 10, a DC component from LPFlt of the detection output from the synchronous detector 7 is used. The other configurations are equivalent to the first example, and their explanation will be omitted.

Now, when a signal with a spectrum as shown by the arrow in FIG. 3 is received (in the figure, this is the selection characteristic of the 40iBPF 4), the output from the synchronous detector 7 is expressed by the following equation.

f(I!111a)IIω. t;Aoos2ω. 10B
OOIIω. t11aO8(ω.+Δtn)t=4'z
+ (A/2) cos2ω, t+ (B/2)
oos (2ω.+Δω)t+(Ruri(2)Δω・・(
31 By passing the signal of equation (3) through the LPF, (M
2) The following DC component can be extracted. That is,
The output of LPFII (Ay/2) is completely proportional to the received signal. Therefore, if the gain of the IF amplifier 10 is controlled according to the signal level of (A/2i), the I
The output level of the F angle lO is always kept constant, making it possible to eliminate the influence of interference waves.

Here, the gain control width of IF amplifiers 5 and 10 is set to 40
dB, about 10 dB, the PLL circuit 8 can obtain a signal synchronized with the IF carrier. Since the gain control is sufficiently performed in step 5, fluctuations in the AM demodulation output level are reduced.

FIG. 4 is a circuit diagram of a specific example of the IF amplifier 10, synchronous detector 7, and LPFs 9 and 11 in the block of FIG.

In the figure, an IF amplifier 10 is configured by transistors Q1 to Q4, resistors to R9, and a current source.
An IF multiplied signal is applied to the base of the transistor Q from the IF amplifier 5 in the previous stage via the capacitor C0. A synchronous detector 7 is configured by the transistors Q5 to Q1o and the current source 2, and the transistors Q5. A transistor Q, which is the output of the IF amplifier 10, is connected between the base of Q6.
The collector output of Q2 is applied. and the common base of transistor Q7 + qlO and Q8. A signal synchronized with the IF carrier is applied from the PLL circuit 8 to the common base of Q9. Transistor Q61QIO
To the common collector of, Germany. , LP by capacitor C3
F9 is connected, and transistor Q7. LP is connected to the common collector of Q9 by resistor R5 and capacitor fC2.
FI 1 is connected. The output of this LPFII is I
This is a base control signal for the transistor Q4 of the F amplifier 10.

The gain A7 of the IF amplifier 10 is AV=yrrL-R3#(engine q/(2kT)l-R3・
・・・・・・・・・・・・(4) (R3=R4
It can be seen that the gain AV changes by changing the current flowing through the transistor Q3. To change this process, transistor Q3. It is sufficient to change the shunt ratio of the current source I□ by Q4, and for this purpose, the transistors Q7 . The DC component of the common collector output of Q9 is extracted by LPFII to control the base voltage of transistor Q4.

FIG. 5 is a circuit diagram showing a specific example of a part of the block shown in FIG. 2. In the example shown in Fig. 4 above, the fl, IF amplifier, and synchronous detector are separated and provided independently, but the IF amplifier (amplifier indicated by 10 in Fig. 4) is omitted, and the current source of the synchronous detector is omitted. The circuit shown in FIG. 5 is an example of a circuit in which the current is changed (indicated by d in FIG. 4).

The synchronizing signal from the PLL circuit 8 is transmitted to the transistor Q1□,
It is applied between the common base of Q14 and the common base of transistors QL21 and Q13, and an IF times signal is applied from IF Ang5 to the base of transistor Q15 via capacitor C4. And transistors Q1□, Q18
The current source I3 is shunted by the current source I3, and this shunt control is performed by a signal passed through the buffer transistor Q of the synchronous detection output (common collector output of the transistors Q1 and Q14). That is, the buffer transistor Q
The emitter output of 19 is applied via the resistor R14 to the LPF formed by the capacitor C6 and the resistor R15, and this LPF
The output is used as the base control signal of transistor Q18, and the synchronous detection output level is controlled according to the DC component level of the synchronous detection output, and it is clear that it has the same effect as the example in Figure 4. It is.

Effects of the Invention As described above, according to the present invention, the level control of the I2 stage can be controlled by two steps.
The process is divided into stages, with the first stage having an IF/bell level detection output, and the second stage having a synchronous detection output, making it possible to reduce gain suppression due to interference waves and improve synchronization of the PLL circuit. This means that fluctuations in the demodulation level between time and asynchronous time can be made small. Further, there is an effect that variations in the steady-state gain of the IF amplifier 5 in the previous stage can be absorbed by the gain control in the IF amplifier 10 in the latter stage.

[Brief explanation of the drawing]

Figure m1 is a block diagram of a conventional AM receiver, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a diagram showing an example of the reception frequency spectrum in the I2 stage, and Figures 4 and 5 are FIG. 2 is a circuit diagram showing a specific example of a part of the block in FIG. 2; Explanation of symbols of main parts

Claims (3)

[Claims] (1) Gain control means for detecting the output level of an intermediate frequency amplifier and controlling the gain of the intermediate frequency amplifier according to the detected output, and synchronously detecting an AM signal using the gain-controlled intermediate frequency signal output. AM including a synchronous detection means for
AM receiver, comprising level control means for further controlling the level of the gain-controlled intermediate frequency signal output according to the synchronous detection output of the synchronous detection means.
Receiving machine. (2) The AM receiver according to claim 1, wherein the level control width by the gain control means is set larger than the level control width by the level control means. (3) The AM receiver according to claim 1 or 2, wherein the detector for detecting the output level of the intermediate frequency amplifier is an envelope detector.