JPS6190445A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6190445A JPS6190445A JP21210784A JP21210784A JPS6190445A JP S6190445 A JPS6190445 A JP S6190445A JP 21210784 A JP21210784 A JP 21210784A JP 21210784 A JP21210784 A JP 21210784A JP S6190445 A JPS6190445 A JP S6190445A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- film
- titanium
- nitride
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- -1 tungsten nitride Chemical class 0.000 claims description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims 1
- 239000003870 refractory metal Substances 0.000 claims 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000010936 titanium Substances 0.000 abstract description 10
- 229910052719 titanium Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に半導体装置ηの配線層に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring layer of a semiconductor device η.
従来、半導体装置の電極配線は第２図に示されるような
構造が一般的であシ、１は半導体基板。Conventionally, the electrode wiring of a semiconductor device generally has a structure as shown in FIG. 2, where 1 is a semiconductor substrate.
２は１層目の電気絶縁膜である。電気絶縁膜４は電極配
線３を機械的、化学的に保ＩＪする膜である。2 is the first layer of electrical insulating film. The electrical insulating film 4 is a film that mechanically and chemically protects the electrode wiring 3.
多層配線構造の場合、電気絶縁膜４は層間絶縁膜に相当
する。電極配線３の材料にはアルミ、ニウム或はアルミ
ニウムとシリコン、銅などの合金が広く用いられている
が、このような従来の半導体装置に３００℃以上の熱処
理を施すと、第３図に示す空洞５が電極配線３の内部、
特に周辺部に多く発生する。空洞５は熱処理が高温、長
時間であるほど大きくなる。空洞５の発生は電極配線３
の内部９表面または電気絶縁膜４の内部に存在するＨ２
Ｏ＊ Ｎ２ ＊ ＣＯ＊ Ｈ２等のガスが原因と思われ
るが、詳細は明らかではない。In the case of a multilayer wiring structure, the electrical insulating film 4 corresponds to an interlayer insulating film. Aluminum, nium, or an alloy of aluminum, silicon, copper, etc. is widely used as the material for the electrode wiring 3. When such a conventional semiconductor device is subjected to heat treatment at a temperature of 300°C or higher, it becomes as shown in Fig. 3. The cavity 5 is inside the electrode wiring 3,
It occurs especially in the peripheral areas. The cavity 5 becomes larger as the heat treatment is performed at a higher temperature and for a longer time. Cavity 5 occurs due to electrode wiring 3
H2 existing on the internal surface 9 or inside the electrical insulating film 4
Gases such as O*N2*CO*H2 are thought to be the cause, but the details are not clear.
以上のように従来の半導体装置は、熱処理後電極配線の
内部や周辺部に空洞が生じるので、１１Ｌ流容量が不足
したシ断線の原因となっていた。本発明はかかる問題点
に鑑みてなされたものであり、高温長時間の熱処理にお
いても安定した電極配線を備える高信頼性の半導体装置
を得ることを目的とする。As described above, in the conventional semiconductor device, cavities are formed inside and around the electrode wiring after heat treatment, which causes disconnection due to insufficient 11L flow capacity. The present invention has been made in view of such problems, and an object of the present invention is to obtain a highly reliable semiconductor device having electrode wiring that is stable even during heat treatment at high temperatures and for a long time.
本発明は、第１の電気絶縁膜と第２の電気絶縁膜との間
に配線層を有する半導体装置において、配線層は少なく
とも高融点金属の窒化物膜とアルミニウム或はアルミニ
ウム合金膜とからなることを特徴とする。The present invention provides a semiconductor device having a wiring layer between a first electrical insulating film and a second electrical insulating film, wherein the wiring layer is made of at least a nitride film of a high melting point metal and an aluminum or aluminum alloy film. It is characterized by
以下図面を参照して本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
８１図（ａ） 、 （ｂ） −（ｃ）は本発明の実施例
に係る半導体装置の製造プロセスの概略を示す図であシ
、６はシリコン基板、７はシリコン酸化膜、８はチタン
。81(a), (b) to (c) are diagrams schematically showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, in which 6 is a silicon substrate, 7 is a silicon oxide film, and 8 is a titanium film.
９は窒化チタン、１０はアルミニウム、１１はシリコン
窒化膜である。9 is a titanium nitride film, 10 is an aluminum film, and 11 is a silicon nitride film.
次に製造プロセスを説明すると、まず周知の拡散・酸化
法を用いてシリコン基板１の一主面上にＰ型及びＮ型導
電領域を形成する（図示せず）。Next, the manufacturing process will be described. First, P-type and N-type conductive regions are formed on one main surface of the silicon substrate 1 using a well-known diffusion/oxidation method (not shown).
次に主面を被覆するシリコン酸化膜７に電極域シ出し開
孔を設けた後チタン８．窒化チタン９及びアルミニウム
１０を順次被着する。チタン８はＰ型及びＮ型導電領域
とのオーム接触のための膜である。窒化チタン９は、窒
素を含む雰凹気中でチタンをスパッタするいわゆる反応
性スパッタ法で被着してもあるいは窒化チタンのターゲ
ットをスパッタしても被着しても良い。またアルオニウ
ム１０の代シニアル電ニウムーシリコン、アルをニウム
−銅あるいはアルン二つムーシリコンー銅などの合金を
用いても良い（第１図（ａ））。Next, holes are formed in the silicon oxide film 7 covering the main surface to expose the electrode area, and then titanium 8. Titanium nitride 9 and aluminum 10 are sequentially deposited. Titanium 8 is the membrane for ohmic contact with the P-type and N-type conductive regions. The titanium nitride 9 may be deposited by a so-called reactive sputtering method in which titanium is sputtered in an atmosphere containing nitrogen, or by sputtering a titanium nitride target. Further, an alloy such as 10-alonium-silicon-alonium-silicon, 1-aluminum-copper, or 2-aluminum-silicon-copper may be used (FIG. 1(a)).
次にアルオニウム１０上にホトレジストパターンを形成
し、アルオニウム１０．窒化チタン９及びチタン８を順
次選択蝕刻し、第１層配線を得る０この時の蝕刻は四塩
化炭素を含むガスプラズマによる反応性イミンエツチン
グ法を用いると、第１層配線を構成する３種類の膜が蝕
刻できるので好適で゛ある（第１図伽））。Next, a photoresist pattern is formed on the Alonium 10. Titanium nitride 9 and titanium 8 are sequentially selectively etched to obtain the first layer wiring.If a reactive imine etching method using a gas plasma containing carbon tetrachloride is used for this etching, three types of the first layer wiring are formed. This method is suitable because the film can be etched (Fig. 1)).
次にチタン８．窒化チタン９及びアルミニウム１０から
なる第１層配線を含むシリコン基板６にシリコン窒化膜
１１を被着し、該シリコン窒化膜１１に外部取り出し電
極開孔（図示せず）を設けて本発明の半導体装置を、得
る（第１図（Ｃ））。Next, titanium 8. A silicon nitride film 11 is deposited on a silicon substrate 6 including a first layer wiring made of titanium nitride 9 and aluminum 10, and an external lead-out electrode hole (not shown) is provided in the silicon nitride film 11 to form a semiconductor of the present invention. A device is obtained (FIG. 1(C)).
かかる膜の構成によれば５０６℃・１時間程度め熱処理
を施しても空洞は全く発生しない。According to the structure of such a film, no cavities are generated even after heat treatment at 506° C. for about 1 hour.
第３図は本あ明の第２の実施例に係る半導体装置の断面
図であシ、第１図のチタン８の代、？に白金シリサイド
１２を用いたものである。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention. In this case, platinum silicide 12 is used.
第４図は本発明の第３の実施例に係る半導体装置の断面
図であシ、２層配線構造となっている。FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention, which has a two-layer wiring structure.
１３．１４．ｘｄはそれぞれ２層目の窒化チタン。13.14. xd is the second layer of titanium nitride.
アルミニウム、シリコン窒化膜である。Aluminum, silicon nitride film.
第５図は本発明の第４の実施例に係る半導体装置の断面
図であシ、１５はシリコン基板１とチタン８の間に配置
されたシリコン膜である。FIG. 5 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and 15 is a silicon film disposed between silicon substrate 1 and titanium 8. In FIG.
第６図は本発明の第５の実施例に係る半導体装置の断面
図であ）、窒化チタン９に対してアルオニウム１０のパ
ターンを縮少しアルミニウムの量に対する窒化チタンの
址を増大させ、本発明の効果を更に大きくした例である
。FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention), in which the pattern of Al onium 10 is reduced relative to titanium nitride 9 to increase the amount of titanium nitride relative to the amount of aluminum, and the present invention This is an example of further increasing the effect of .
以上説明したように、本発明によれば配線用のアルオニ
ウムが細った）断線したシしないので、所定の電流容量
を得ることができるとともに、信頼度の高いものを得る
ことができる。As explained above, according to the present invention, since the aronium for wiring does not become thin and disconnected, it is possible to obtain a predetermined current capacity and to obtain a highly reliable one.
【図面の簡単な説明】
８１図（ａ） 、 （ｂ） 、 （ｃ）は本発明の実施
例に係る半導体装置の製造プロセスを説明する図であり
、第２図（ａ） 、 Ｏｎ）は従来例に係る半導体装置
の製造プロセスを説明する図である。第３図〜第６図は
本発明の別の実施例に係る半導体装置を示す図である。
１・・・半導体基板、２．４・・・電気絶縁膜、３・・
・電極配線、 ５・・・空洞、６・・・シリコン基板
、７・・・シリコン酸化膜、８・・・チタン、９．１３
・・・窒化チタン、１０．１４・・・アルミニウム、
１１．１５・・・シリコン窒化膜、
１２・・・白金シリサイド、
１６・・・シリコン膜。
第 １ａ ｍ
第１ｂ図
第１ｃ図
第 ２ａ 図
第２ｂ図
第３図
第 ４ 図
第６図[Brief Description of the Drawings] Figures 81 (a), (b), and (c) are diagrams for explaining the manufacturing process of a semiconductor device according to an embodiment of the present invention, and Figures 2 (a) and (On) FIG. 2 is a diagram illustrating a manufacturing process of a semiconductor device according to a conventional example. 3 to 6 are diagrams showing semiconductor devices according to other embodiments of the present invention. 1... Semiconductor substrate, 2.4... Electrical insulating film, 3...
・Electrode wiring, 5... Cavity, 6... Silicon substrate, 7... Silicon oxide film, 8... Titanium, 9.13
...Titanium nitride, 10.14...Aluminum, 11.15...Silicon nitride film, 12...Platinum silicide, 16...Silicon film. Fig. 1a m Fig. 1b Fig. 1c Fig. 2a Fig. 2b Fig. 3 Fig. 4 Fig. 6
Claims (1)
を有する半導体装置において、 （１）前記配線層は少なくとも高融点金属の窒化物膜と
アルミニウム或はアルミニウム合金膜とからなることを
特徴とする半導体装置。 （２）前記高融点金属の窒化物膜パターンは、前記アル
ミニウム或はアルミニウム合金膜パターンと同一か或は
大きいことを特徴とする特許請求の範囲第１項に記載の
半導体装置。 （３）前記高融点金属の窒化物は、窒化チタン、窒化タ
ングステン、窒化モリブデン、窒化タンタルであること
を特徴とする特許請求の範囲第１項に記載の半導体装置
。[Scope of Claims] A semiconductor device having a wiring layer between a first electrical insulating film and a second electrical insulating film, wherein: (1) the wiring layer is made of at least a nitride film of a high melting point metal and aluminum or A semiconductor device comprising an aluminum alloy film. (2) The semiconductor device according to claim 1, wherein the refractory metal nitride film pattern is the same as or larger than the aluminum or aluminum alloy film pattern. (3) The semiconductor device according to claim 1, wherein the high melting point metal nitride is titanium nitride, tungsten nitride, molybdenum nitride, or tantalum nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21210784A JPS6190445A (en) | 1984-10-09 | 1984-10-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21210784A JPS6190445A (en) | 1984-10-09 | 1984-10-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6190445A true JPS6190445A (en) | 1986-05-08 |
Family
ID=16616992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21210784A Pending JPS6190445A (en) | 1984-10-09 | 1984-10-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190445A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS633436A (en) * | 1986-06-23 | 1988-01-08 | Nec Corp | Manufacture of semiconductor device |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPS6459937A (en) * | 1987-08-31 | 1989-03-07 | Sony Corp | Semiconductor device |
| JPH0282532A (en) * | 1988-09-19 | 1990-03-23 | Mitsubishi Electric Corp | Pad structure of semiconductor device |
| JPH02203528A (en) * | 1989-02-01 | 1990-08-13 | Hitachi Ltd | Specimen postpocessing and device therefor |
| JPH02299269A (en) * | 1989-05-15 | 1990-12-11 | Nec Corp | Al-cu/tin electrode wiring structure |
| JPH0316126A (en) * | 1989-03-10 | 1991-01-24 | Hitachi Ltd | Sample processing method |
| JPH0362520A (en) * | 1989-07-31 | 1991-03-18 | Hitachi Ltd | Plasma cleaning method |
| US5313101A (en) * | 1990-08-28 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Interconnection structure of semiconductor integrated circuit device |
| US5341026A (en) * | 1991-04-09 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a titanium and a titanium compound multilayer interconnection structure |
| US5348376A (en) * | 1992-04-21 | 1994-09-20 | Tachi-S Co., Ltd. | Arrangement of headrest on a seat |
| US6051490A (en) * | 1991-11-29 | 2000-04-18 | Sony Corporation | Method of forming wirings |
| US6268290B1 (en) * | 1991-11-19 | 2001-07-31 | Sony Corporation | Method of forming wirings |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101454A (en) * | 1981-12-12 | 1983-06-16 | Nippon Telegr & Teleph Corp <Ntt> | Electrode for semiconductor device |
| JPS59100565A (en) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | Semiconductor device |
-
1984
- 1984-10-09 JP JP21210784A patent/JPS6190445A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58101454A (en) * | 1981-12-12 | 1983-06-16 | Nippon Telegr & Teleph Corp <Ntt> | Electrode for semiconductor device |
| JPS59100565A (en) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | Semiconductor device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS633436A (en) * | 1986-06-23 | 1988-01-08 | Nec Corp | Manufacture of semiconductor device |
| JPS6441240A (en) * | 1987-08-07 | 1989-02-13 | Nec Corp | Semiconductor integrated circuit device |
| JPS6459937A (en) * | 1987-08-31 | 1989-03-07 | Sony Corp | Semiconductor device |
| JPH0282532A (en) * | 1988-09-19 | 1990-03-23 | Mitsubishi Electric Corp | Pad structure of semiconductor device |
| JPH02203528A (en) * | 1989-02-01 | 1990-08-13 | Hitachi Ltd | Specimen postpocessing and device therefor |
| JPH0316126A (en) * | 1989-03-10 | 1991-01-24 | Hitachi Ltd | Sample processing method |
| JPH02299269A (en) * | 1989-05-15 | 1990-12-11 | Nec Corp | Al-cu/tin electrode wiring structure |
| JPH0362520A (en) * | 1989-07-31 | 1991-03-18 | Hitachi Ltd | Plasma cleaning method |
| US5313101A (en) * | 1990-08-28 | 1994-05-17 | Mitsubishi Denki Kabushiki Kaisha | Interconnection structure of semiconductor integrated circuit device |
| US5488014A (en) * | 1990-08-28 | 1996-01-30 | Mitsubishi Denki Kabushiki Kaisha | Interconnection structure of semiconductor integrated circuit device and manufacturing method thererfor |
| US5341026A (en) * | 1991-04-09 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a titanium and a titanium compound multilayer interconnection structure |
| US6268290B1 (en) * | 1991-11-19 | 2001-07-31 | Sony Corporation | Method of forming wirings |
| US6051490A (en) * | 1991-11-29 | 2000-04-18 | Sony Corporation | Method of forming wirings |
| US5348376A (en) * | 1992-04-21 | 1994-09-20 | Tachi-S Co., Ltd. | Arrangement of headrest on a seat |
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