JPS6213128A - Error correction system - Google Patents

Abstract

PURPOSE:To attain sufficiently the correction capability of an error correction code by applying error correction to one code word and revision to an error flag while being divided into two stages of accessings so as to attain a complicated correcting method and error flag processing. CONSTITUTION:In the 1st access, each data constituting a code word and an error flag corresponding to the data are read from memory RAMs 3, 17 and the error pattern and location are obtained by using the error flag and the syndrome, the error flag is stored tentatively in a register 20, and in the 2nd access, each data constituting the code word is read again and the error flag corresponding to the data is obtained from the register 20, and according to the method decided by the 1st access, the data is corrected while the erroneous data is accessed and the result is written in the same address of the RAM 3. When the 2nd access is finished, the revised value of the error flag is decided, the result is stored tentatively and the storage content is written in the RAM 17 during the 2nd access period when the next code word is subjected to error correction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for error correction of data to which an error flag has been added and for updating the error flag after the correction. This invention relates to a method for repeatedly correcting errors in encoded data.

First, the error correction code used in the explanation of the error correction method according to the present invention will be explained. The Reed-Solomon code used here is a code word that is created by adding two check data P and Q to the information data W-(j=], 2..., n-2) with a code length of n. Configure. P and Q are generated to satisfy the following equation.

That is, 1''-α 1+α However, the addition is modulo 2, each data consists of m bits, and α is a primitive element on the Galois field GF (2'rn). If an error occurs in the codeword, it is corrected as follows.

Syndromes SP and SQ defined as below are calculated for information data and inspection data containing errors.

If there is no erroneous data, S, -5Q=O.

The error in the two information data is at position j (1≦j<k≦
n-2), and as a result, Wj and Wk become -Wj+gj and We-Wk+ek, respectively. However, ej+11'k is the error pattern of Wj and Wk. At this time, SP and SQ are as follows.

e・+αn−k.

This is it':) Calculating e j + e k However, addition is modulo 2 (8, so it is the same as subtraction.

Therefore, error positions j, k are determined in advance by other means.
If , is determined, ej and Pk can be determined using the above equation, and error correction becomes possible. In addition, if an error in one information data occurs at position j, and the error pattern is ej, then in Equation 2, e k = O, SP-6j From this, SQ In this case, even if position j is not determined in advance, SP,
Since j is obtained by obtaining αj from S, and ej is SP itself, error correction is possible.

As explained above, a lead with two test data
In the Solomon code, for a data error in a code word, two pieces of data can be corrected if the position of the error is known, and one piece of data can be corrected if the position of the error is not known. Furthermore, although only the error in the information data W has been described, the same applies to the errors in the information data P and Q, and it is sufficient to treat P as the (n-1)th data and Q as the nth data.

Conventionally, there are PCM recorders that use Reed-Solomon codes as error correction codes, and PCM recording adapters for home VTRs use b-adjacent codes similar to Reed-Solomon codes.

In such a PCM audio data error correction device, error correction is performed while supplying audio data to D/A conversion at a constant audio sampling frequency cycle, so pre-correction processing such as syndrome calculation is more expensive than correction. It needs to be done quickly.

In addition, PCM audio data has a strong correlation with the data before and after it, and if it cannot be corrected, the effect of the error can be reduced by processing such as average value interpolation as long as the error can be detected. The error correction method and error flag processing are simple, and the error correction is not often repeated.

However, such an error correction device is not suitable for error correction of digital data such as general computer tagograms other than PCM audio. This is because the digital
In data, error correction is more important than error detection, and multiple codes are used to multiplex error detection coding and error correction coding, and error correction is repeated until the error is corrected to the limit of the ability of each error correction code. This is because complicated correction methods and error flag processing must be performed. Also,
In the case of such digital data, it is not necessarily necessary to perform error correction while transmitting the data, so the restrictions on operation timing are more relaxed than in the case of PCM audio data.

The present invention is particularly suited to complex error correction and error flag processing of general digital data that has been subjected to multiple error detection encoding and error correction encoding, which cannot be handled by the error correction apparatus for PCM audio data as described above. It is an object of the present invention to provide an error correction method that allows processing to be performed with a relatively simple circuit configuration.

The error correction method according to the present invention associates an error flag consisting of at least one bit with each data to indicate a predetermined error state, and identifies the data to be corrected and each data stored in the memory. The error flag corresponding to the code word is accessed twice in succession for each code word to correct errors in the data constituting one code word, and at the same time, the error flag is updated when determining the value of the error flag. It is characterized in that the processing is carried out by temporarily storing it in first and second storage means other than the memory immediately before and after the processing.

Hereinafter, one embodiment of the present invention will be described based on the accompanying drawings. FIG. 1 shows an example of an error correction device that implements the method of the present invention, where ■ is a data input/output terminal, 2 is a data bus, and 3 is a data RA in which data before and after error correction is stored.
M, 4 is an α multiplier that multiplies data by α11, 5 is 2
A 5α nested αB calculation circuit outputs a nested αB for two input signals A and B, and the output of 5a is input, and its output is 5α.
S consisting of a first D flip-flop 5b serving as the B input of a.

The calculation circuit 6 is composed of the first adder of 6a and the output of 6a, and its output is the second D flip-flop 6b which is one input of 6(L). The second adder that adds the outputs, 8 adds the output of 7 to 1+αj−
"1+αj-' divider for division, 9 is an AND gate that outputs the AND logic of the output of 6 and the control signal of 20, 10
is the third adder that adds the outputs of 8 and 9, 11 is the fourth adder that adds the data of the output of 3 and the output of 10, and 12 is the 1st adder.
3 controlled by 23 to latch the output of 1 and become valid only when its output is written to 3.
A state D flip-flop, 13 is a 10th detection circuit that detects that all bits of the output of 5 and 6 are n□11, and 14 is a detection circuit that detects that all bits of the output of 7 are 0''. 20 detection circuit for detecting, 15 an error/) lag input/output terminal, 16 an error flag bus, 17 an error flag for storing error flags before and after error correction.
A flag RAM 18 is an error counter for calculating the number of error flags indicating the presence of an error among the error flags corresponding to each data in a code word. The -j counter 20 is used to obtain the value of -j when the error flags of the two data indicate the presence of an error. flag register,
21 determines the data to be corrected by referring to the outputs of 1.3, 14, and 18 and the error flags of each data, notifies it to 27, and sends a timing signal to 5b from 27 as necessary. A correction control circuit 22 is 1.3 and 1.4 for stopping and further controlling 9.
, 1. An error flag determination circuit that determines the value of the error flag to be updated and written to 17 after correction by referring to the output of 8 and the error flag of each data, 2
3 is an error flag register 24 that launches the error flag output from the error flag determination circuit 22;
3, 17, and 27 are address counters that output addresses corresponding to each data and error flag, 25 is an address latch that latches the address output from the address counter 24, and 26 is an address counter 24.
a selector that selectively outputs one of the output of the address latch 25 and the output of the address latch 25, 27 is 2], , 24
, 28 outputs and clocks are input, and various timing signals and control signals are generated based on the clocks.
In addition to controlling the timing signals, each circuit in the figure
Timing control circuit for sending control signals, 28
29 is an access counter indicating the current access in the correction of one code word, and 29 is a clock input terminal.

In the figure, the data read from data RA, M3 is corrected by a correction circuit composed of 4 to 12, and the structure of this correction circuit itself has been used in the past. Rather, the feature of the present invention lies in the operation of the entire error correction device and its timing and control.

Next, the operation of the apparatus shown in FIG. 1 will be explained. FIG. 2 is a timing diagram showing the operation of FIG. 1.

In the initial state, the timing control circuit 27 in FIG. 1 sets the contents of 5b, 6b, 1.8, and 19 to 0.
The address counter 24 is set to the address of the first data of the code word to be corrected, and the access counter 28 is placed in the first access state.

In addition, data RAM 3 and error flags RA and M1
It is assumed that data and error flags input from the data input/output terminal 1 and the error flag input/output terminal 15 are written in advance in 7.

Furthermore, the error flag of the previous subblock is latched into the error flag register 20. Thereafter, the contents of this error flag register 20 are held until the end of the second access.

In the first access, the address counter 24 counts up one by one from the address of the first data in accordance with the timing signal from the timing control circuit 27, and the data RAM 3 counts up from the first data W to the last data Q. Output in order. The output data is multiplied by α1-71 in α1' multiplier 4, and then A+α
through the B arithmetic circuit 5a and the first D flip-flop 5b.
is latched by a timing signal from the timing control circuit 27. Since the input signal B is 0'' in the initial state, the contents of the first D flip-flop 5b are α11W1.α1'L( 1w1+w2
),...... Therefore, finally α
S, becomes the content of the D flip-flop 5b. The data output from the data RAM 3 passes through the first adder 6a and is similarly latched into the second D flip-flop 6b.

Since the circuit consisting of 6a and 6b sequentially adds and latches the input data, the final content of the second D flip-flop 6b is as follows. When the contents of the SQ calculation circuit 5 and S, and the calculation circuit 6 become α1 HI S and SP, respectively, the 10th detection circuit 13
is 5Q=SP=0 or not, that is, syndrome S,
, S, it is determined whether an error has been detected or not, and the result is latched by the timing signal from the timing control circuit 27. address counter 24
The output of is sent to the error flag RAM via the selector 26.
17 and error flag RA, M 1
．． 7 outputs an error flag corresponding to the output data of the data RAM 3 at the same time as the data. The error flag output from this error flag RAM]7 is the error flag.
At the same time as the error is latched into the flag register 20,
The data is input to the counter 18, and the error counter 18 counts the number of error flags indicating that the data is erroneous based on the timing signal from the timing control circuit 27. At this time, the -j counter 19 counts the number of data until the output of the error counter 18 changes from 1'' to '2'' using the timing signal from the timing control circuit 27. j+k(j<
If the error flag corresponding to the data at position k) indicates an error, the output will be -j. At the end of the first access, the outputs of the error counter 18 and -j counter 19 are determined, and the correction control circuit 21 composed of a combinational logic circuit outputs the outputs of the 10th detection circuit 13 and the error counter 18. Determine the method for determining the error pattern and position. The logic of this decision is, for example, as follows.

1. When the output of the error counter 18 is 0°, if the output of the 10th detection circuit 13 indicates an error, the position determined by the 20th detection circuit 14 is set as the error position, and the SP calculation circuit 6 Let the output of be the error pattern. The 20th detection circuit 14 indicates the position of one error data obtained from the syndromes SP and SQ, as will be described later.

2. When the output of the error counter 18 is 1'' or 3'' or more, if the error flag corresponding to the data at the position determined by the 20th detection circuit 14 indicates an error, that position is set as the error position. Let the output of the SP calculating circuit 6 be an error pattern.

3. When the output of the error counter 18 is 1121+, the positions of the two data whose corresponding error flags indicate an error are set as the error positions, and the two error patterns are S, the calculation circuit 6 and the SP calculation circuit 5. Obtained from the output of

Note that during the first access, the error flag RAM 17 is in a read state.

When the first access is completed, the timing control circuit 27 immediately puts the access counter 28 into the second access state, and at the same time sets the address counter 24 again to the address of the first data, and subsequently starts the second access. In the second access, the timing control circuit 27 sends a control signal to the α1' multiplier 4 to set its output to 0'', and the second D flip-flop 6b, error counter 18, h- J Stop sending the timing signal to the counter 19.As mentioned above, the method of determining the error pattern and the error position differs depending on the output value of the error counter 18, so there are two methods: when the output value is 1" and when the output value is W2T+. The operation during the second access period will be described below. Incidentally, when the value of the output of the error counter 18 is ``3'' or more across 0°', it is basically the same as the case where it is 1''.

FIG. 2(a) shows that the output value of the error counter 18 is II.
This is the case of I II. S at the start of the second access
The output of the Q calculation circuit 5 becomes α1'LS, and since the input signal A is always 0'', the output of the SQ calculation circuit 5 becomes α1'LS every time the timing signal is input from the timing control circuit 27. Multiplied by α.

This timing signal is synchronized with the data output from the data RAM 3, so that the data RAM 3 is in W4.
When outputting W2...P and Q, the output of calculation circuit 5 is α1'S α21S6. ...αS6. It changes to S.

If the output value of the Q error counter 18 is °°1'',
While data RA-M 3 is reading data, the position of one error data is determined from syndromes SP and SQ. That is, if W is mistakenly set to w', -w, 10e- and ZZ, then 5P=e, s, -αn-i, and data RAM 3 outputs W'. When S, the output of the calculation circuit 5 is α''S, so the output SP+α74SQ of the second addition circuit 7 is 60''', and the output of the 20th detection circuit 1 is
4 detects this 0゛', the data RAM
It can be seen that the data W; which No. 3 is currently outputting is incorrect. W if there is one error data; otherwise 11
01+ is not detected. When the 20th detection circuit 14 detects 0'', the correction control circuit 21 refers to the output of the error flag register 20, and if the error flag corresponding to W- indicates an error, the correction control circuit 21 detects the error data in the code. It judges that there is only one TJJ', opens the AND gate 9, inputs 5P=e to the third adder 10, and sends a signal instructing the timing control circuit 27 to make a correction. At this time, since the input of the 1+αj-7 divider 80 is 0'', its output is also 0'', and the third adder 1
The output of 0 is e. This output is added to the output W' of data RAM $3 in the fourth adder 11, and W, +e, -W, +e, -
The output of the fourth adder 11, which outputs 4-e, -, is latched into a three-state D flip-flop 12, which is error corrected.

It is assumed that the timing signal for latching is always supplied from the timing control circuit 27. When the timing control circuit 27 receives a signal instructing correction, the 3-state D flip-flop 12 outputs W,
After latching, a control signal to enable the output is sent to this, and a control signal to put the data RA, M3 into the write state is sent.
The corrected W is written to the address where W was stored. In the above operation, the processing from the detection of 0'' by the 20th detection circuit 14 to the writing of W into the data RAM is performed within one address period corresponding to W+.

Figure 2 (6) shows that the output value of error counter 8 is 11.
In this case, the position of the data corresponding to two error flags indicating an error among the error flags read from the error flag register 20 is determined as the error position. This error position is defined as i, k (j<k
), and Wj and Wk are mistakenly ヅ1-Wj〇ej, respectively.
, Wk-Wλ10ek, then 5P-ej
-I-ek, S, = αn-je 1 αn-k ,,
It becomes k. When the data RAM 3 is outputting W′j, the output of the SQ calculation circuit 5 is αj1S−e・tenαj−k
From Q,7, which is ek, the output SP+αj1SQ of the second adder 7 is input to the ej ten divider 18. On the other hand, the value of -j obtained in the first access is input to the divider from the -j counter 19, and when division is performed according to this, the output is (1+α""')ek/( ] tenαj−k)−ek
becomes. In the second access, the correction control circuit 21 observes the error flags input from the error flag register 20, and first the error flag indicating an error, that is, the error flag of W' is input. Then, the same circuit opens AND gate 9 and outputs 5P-ej+
It inputs ek to the third adder 10, and instructs the timing control circuit 27 to make a correction and stop sending the timing signal to the first D slip-flop 5b.

At this time, the output of the third adder 10 becomes ek+5P=ej, which is added to W'- in the fourth adder 11 and becomes ek+e
j = Wj + ej + ej - Wj and the error is corrected Wj
is obtained, which is a 3-state D flip-flop 12
K.

After being latched, it is written into data RAM 3 replacing W3. The timing control circuit 27 operates the 3-state D free knob flop 1 according to the correction command.
2 is enabled and the data RAM 3 is placed in a write state, and from then on, transmission of the timing signal to the first D flip-flop 5b is stopped.

Therefore, the output of the S calculation circuit 5 is held to -1 of αj1SQ, and the output of the divider 8 remains eIc.The correction control circuit 21 sets an error flag indicating the second error, that is, a When the error flag is input, the AND gate 9 is closed and a correction is commanded to the timing control circuit 27. At this time, the output ek of the divider is directly output from the third adder 10 to 1+αj-. Then, the fourth adder 11 adds ek to the output WA of the data RAM 3 to obtain Wl + e k=Wk+
Obtain e k+ e k= Wk. This error-corrected Wk is written to the data RAΔ, T3 in the same way as Wj, replacing it with a blank. At the end of the second access, the output of the error flag determination circuit 21 is determined.

The logic of this decision is, for example, as follows.

1. When the output of the error counter 8 is "0", the output of the 10th detection circuit 13 indicates an error, and the 20th detection circuit 14 detects "0" during the second access period. If there is no error, set the error flag to a value that indicates an error; otherwise, set the error flag to a value that does not indicate an error.

2. When the output of the error counter 18 is "1", the output of the No. 10 detection circuit 13 indicates an error, and the error flag indicating the error is output from the error flag register 20. If the 20th detection circuit 14 does not detect 0'', the error flag is set to a value indicating an error, and otherwise set to a value that does not indicate an error.

3. When the output of the error counter 18 is 2'', if the output of the 10th detection circuit 13 does not indicate an error, the error flag is set to a value that does not indicate an error; otherwise, it is set to a value corresponding to undeterminable. shall be.

4. When the output of the error counter 18 is equal to or greater than 3'', the error flag is set to a value corresponding to undetermined.

It is assumed that the error flag is determined to be the same value for all data in the code word. The error flag is set to a value indicating an error when erroneous data exists in the code after the second access is completed, and the error flag is set to a value that does not indicate an error when there is a high probability that erroneous data exists. However, the value for undeterminable is used when the probability of the existence of incorrect data cannot be ignored. If it cannot be determined, the error flag is later determined to either indicate or not indicate an error by using another means, for example, another error detection code. Note that in the above example, the error flag requires at least 2 bits in order to assign three values.

During the second access period, the error flag RAM 17 is in the write state, so the error flag output from the error flag register 23 is the error flag RA, M1.7 at the same time as the above error flag calculation is performed.
will be written to. Note that the address of the error/flag RAM 17 is the address of the subblock that is being corrected in the first access, and the address of the previous subblock is stored in the address latch 25 in the second access. The signal in the selector 26 is switched in response to a command from the correction control 21 so that the address of the previous subblock stored in the address latch 25 is used.

When the error correction and error flag updating for one code word are completed and the second access is completed, the timing control circuit 27 controls the first D clip flop 5b, the second D clip flop 6b, and the error flag. The contents of the counters 18 and k-j counter 19 are reset to '0'', the address counter 24 is set to the address of the first data of the next code word, and the access counter 28 is set to the first access state. Start error correction for the codeword. Thereafter, in the same way, all code words in data RAM 3 are corrected and the corresponding error flag RAM is
The error flag in 1.7 is updated, and after completion, the data is output from data input/output terminal 1 and the error flag is updated.
The flag is taken out from error flag input/output terminal 15.

In the above embodiment, the case where the error correction code is a Reed-Solomon code with two pieces of check data is described, but the present invention can be similarly applied to other codes. Although the circuit configuration shown in FIG. 1 is an embodiment using the above-mentioned Reed-Solomon code, various modifications are possible. For example, although the signal flow in the same figure and Figure 2 are drawn in a format in which each bit constituting the data and error flag is processed in parallel, serial processing is also possible, and the error flag RAM 3 and the data flag L? The AM17 may be the same RAM, and the input/output terminals may be divided into data and error flags. Various modifications can be made to the logic of the correction control circuit 21 and the error flag determination circuit 22. For example, the correction control circuit 21 may ignore the output of the No. 10 detection circuit 13, or the error flag determination circuit In No. 22, the same error flag update value is determined for each data in one code word, but the update value may be determined for each data. This is possible, for example, by distinguishing between corrected data and uncorrected data in one code word, but the error flag determination circuit 22 becomes complex.

In addition, although the above embodiment has been described as an error correction device for one error correction code, the present invention is especially useful when repeatedly performing error correction on data that has been multiplexed with error detection and error correction codes using a plurality of codes. Since this is effective, this will be explained below.

FIG. 3 (tZ) shows a basic configuration when error correction of a data block encoded with a plurality of error detection codes and correction codes is performed using an error correction apparatus according to the present invention.

In the figure, each error correction device is configured for each error correction code as shown in FIG. The flag input/output terminals are connected to each other via a 3-state output buffer. However, the error detection device only detects errors and updates error flags. As shown in Figure 3(b), if the transfer of data and error flags between each device is controlled by a buffer so that error detection or correction in each code is performed in cascade, data passes through each error correction device. Since the data is corrected gradually, the processing speed of the total error correction system for data can be increased. However, speeds can be further increased by separating the bus so that connections are made only between adjacent devices. In each error correction, the device according to the present invention refers to the input error flag L7 and performs error correction that fully utilizes the correction ability of the code, and also updates the error flag after the correction. However, it can also perform powerful error correction. When error detection or error correction for each code is performed multiple times rather than once each time, separate devices are used for each time of error detection and error correction, and the operations are performed in cascade as described above. Although the processing speed is fast, the equipment scale of the entire system becomes large. As shown in FIG. 3(C), only one device is used for each code, data and error flags are transferred between devices on the same bus, and by controlling this, error detection and If error correction is performed multiple times, the device scale of the entire system will not increase. It is assumed that the data and error flag are output from 34 after passing through the path an arbitrary number of times. However, the processing speed of the full error correction system is slow.

Note that if error detection and correction are performed multiple times for each code, the overall correction ability is further improved than if it is performed once each time. Furthermore, if the same type of code is used for both the false alarm detection code and the error correction code (for example, a Reed-Solomon code with two check data), all the false alarm detection and error correction can be performed using only one first code. This can be done by an error correction device as shown in the figure. That is, in each error correction, the above-mentioned error correction error flag is updated for each code word for each code used for correction. ! In addition, for each false detection,
By omitting or changing some of the operations of the error correction device, only error detection and error flag updating are performed. Usually, the data constituting one code word is different depending on each code, so the address counter 2 is set for each code.
It is necessary to control the operation of 4, but this requires timing and
This is easily done by the control circuit 27. Therefore, in this case, error detection and error correction using multiple codes can be repeated an arbitrary number of times with a very small equipment scale, and each error correction can be performed with the strong error correction described above. can. Error flag register 20 in the device of FIG.
and 23 can be easily realized by a circuit such as a D flip-flop or a circuit such as a shift register.

Effects of the Invention As described above, according to the present invention, in consideration of the fact that general digital data such as program data does not necessarily require error correction while transmitting the data,
Error correction for one codeword and error flag update are performed in two steps, making it possible to perform complex correction methods and error flag processing, and fully utilize the correction ability of the error correction code. In addition, it is possible to accurately notify the state of the error after correction. Furthermore, since the error flag is temporarily stored and held in the first and second storage means other than the error flag RAM immediately before and after determining the value of the error flag when updating the error flag, the second access At the same time as writing error flags to error flags RA and M, a correction method can be determined or a two-word error (an error where the error flag counter is 1121+) can be corrected, and error flags RA and M can be read and accessed. This means that the time required for error correction of data constituting one code word can be reduced. Furthermore, the device of the present invention can be realized relatively easily. Taking Figure 1 as an example, general-purpose ICs can be used for adders, D flip-flops, counters, etc., and the α1-41 multiplier is RO
M or a combination of gates, ]+αj−” divider can be easily realized using a ROM or a combination of a ROM and a gate, and each two-step operation is performed by regularly accessing the same code word twice. Therefore, timing control within the device is also easy.If the device of the present invention performs error correction on data that has been multiplex encoded using a plurality of codes, in each error correction, the error flag updated after the error correction in the previous stage is Since sufficient correction is performed with reference to the above, very strong error correction can be performed as a whole.

In particular, if multiple codes are all of the same type,
The error correction device of the present invention, which is normally required for each code, can be replaced by one error correction device of the present invention, and the scale of the device is very small. Can be done several times.

At this time, it is necessary to switch the timing control within the device for each code, but this can be done easily.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment, and FIG. 3 is a multiple encoded data block configured using the error correction device of the present invention. FIG. 2 is a diagram showing an example of a total error correction processing system.

Claims (3)

[Claims] (1) An error correction method that corrects errors in code words of an error correction code consisting of information data and check data, and in which at least one error correction method is used to indicate the error state determined in advance.
An error flag consisting of a bit is made to correspond to each data, and the data to be error corrected stored in the memory and the error flag corresponding to each data are accessed twice in succession for each code word. At the same time, the error flag is updated immediately before and after the value of the error flag is determined, and the error flag is temporarily stored in the first and second storage means other than the memory, respectively. An error correction method characterized by memory retention. (2) In the above two accesses, the first access reads out each data forming the code word and the error flag corresponding to the data from the memory, and is the basis for determining the error pattern and position from the data. In addition to calculating the syndrome, a method for determining the error pattern and position is determined based on the error flag and the syndrome, and the error flag is temporarily stored in the first storage means, and in the second access, the code word is read again. Read each data making up the data and set the error flag corresponding to the data to the first
The error pattern is obtained from the storage means, the error pattern is obtained from the syndrome according to the method determined in the first access, the error position is obtained from the syndrome and the error flag, and the data is corrected while the incorrect data is being accessed. After doing this, immediately write to the same address in memory,
Further, when the second access is completed, an updated value of the error flag is determined and temporarily stored in the second storage means, and the stored contents of the second storage means are used for error correction of the next code word. 2. The error correction method according to claim 1, wherein writing to the memory is performed during a second access period. (3) Each data and error in the above two accesses
Claim 1 or 2, characterized in that all flags are accessed at the same addressing timing.
Error correction method described in section.