JPS62201974U - - Google Patents
Info
- Publication number
- JPS62201974U JPS62201974U JP9020786U JP9020786U JPS62201974U JP S62201974 U JPS62201974 U JP S62201974U JP 9020786 U JP9020786 U JP 9020786U JP 9020786 U JP9020786 U JP 9020786U JP S62201974 U JPS62201974 U JP S62201974U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- multilayer printed
- guide pin
- guide pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
Description
第１図は本考案の一実施例におけるガイドピン
の構成説明図、第２図は製造装置の全体構成を表
わした構成説明図である。
２…プリプレグ、４…治具板、５…金型、６…
ガイドピン、１１…複合めつき皮膜、１２…フツ
素樹脂コーテイング皮膜。
FIG. 1 is an explanatory diagram of the configuration of a guide pin in an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the overall configuration of the manufacturing apparatus. 2...Prepreg, 4...Jig plate, 5...Mold, 6...
Guide pin, 11...composite plating film, 12...fluororesin coating film.
Claims (1)
て挾み込み、金型に立設されたガイドピンにより
、多層プリント板と治具板とを所定位置に位置決
めして加熱・加圧せしめるようにした多層プリン
ト回路板の製造装置に用いられるガイドピンおい
て、上記ガイドピンの外表面上にフツ素樹脂が共
析された複合めつき皮膜を形成してなることを特
徴とする多層プリント回路板の製造装置に用いら
れるガイドピン。 The multilayer printed circuit board is sandwiched between the molds via a jig plate, and the multilayer printed circuit board and the jig board are positioned at predetermined positions using guide pins set up in the mold, and then heated and pressurized. A guide pin used in a manufacturing device for a multilayer printed circuit board, characterized in that a composite plating film in which a fluororesin is eutectoid is formed on the outer surface of the guide pin. Guide pins used in printed circuit board manufacturing equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986090207U JPH0234835Y2 (en) | 1986-06-13 | 1986-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986090207U JPH0234835Y2 (en) | 1986-06-13 | 1986-06-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62201974U true JPS62201974U (en) | 1987-12-23 |
| JPH0234835Y2 JPH0234835Y2 (en) | 1990-09-19 |
Family
ID=30949864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986090207U Expired JPH0234835Y2 (en) | 1986-06-13 | 1986-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0234835Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0391296A (en) * | 1989-09-01 | 1991-04-16 | Fujitsu Ltd | Lamination method of multilayer printed wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4735505U (en) * | 1971-05-18 | 1972-12-20 |
-
1986
- 1986-06-13 JP JP1986090207U patent/JPH0234835Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4735505U (en) * | 1971-05-18 | 1972-12-20 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0391296A (en) * | 1989-09-01 | 1991-04-16 | Fujitsu Ltd | Lamination method of multilayer printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0234835Y2 (en) | 1990-09-19 |
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