JPS62204576A - Manufacturing method of vertical transistor - Google Patents

Abstract

PURPOSE:To improve the controllability of electrode dimension while preventing a crystal from deteriorating by a method wherein heat resistant metals and insulating films are laminated on a semiconductor layer making openings down to a semiconductor layer to grow semiconductor layer in the openings only. CONSTITUTION:An N-GaAs wafer as the second semiconductor layer 2 is prepared on an N<+>GaAs substrate as the first semiconductor layer 1 by hydride VPE process and then heat resistant material (base electrode) 3 and SiO2 as an insulating films 4 are laminated respectively by sputtering process and CVD process on the second semiconductor layer 2. Next, after forming resists 5, a grating with a gap of W/SiO2 is formed by reactive ion etching process. Later, after wetetching the surface of GaAs, N<->GaAs is selectively grown by hydride VPE process. An ohmic electrode is formed on a collector electrode 9 to form TiAu on the upper part of collector electrode 9. Finally, SiO2 is removed to insulation-isolate the parts excluding the action layer immediately below the collector electrode by ion-implanting proton.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing ultra-high speed, high frequency vertical transistors.

[Prior art]

As a conventional ultra-high-speed, high-frequency vertical transistor, a permable base transistor (PBT) is known, as shown in FIG. Well, that is because the electrons 10 travel from the emitter electrode 8 to the correct electrode 9 without colliding or scattering several times due to the miniaturization of the element.
The traveling speed of electrons is expected to be several times larger than in the steady state. For this reason, efforts are being made to develop it as a high-frequency, high-speed device that surpasses PBTnGaAs MESFETs.

The operating principle of this device is that n is injected from the emitter electrode 8.
*The amount of electrons 10 flowing into the correct electrode 9 is applied to all the base electrodes 3, the potential near the base electrode is changed, and the amount of electrons 10 flowing into the base electrode 9 is controlled to -i1'. In this structure, the base is connected to the other 3. The upper layer is necessary for operation. In short, is there a compensation between the base and collector? As a structure to further improve high frequency and high speed performance, a vertical transistor without a semi-coupled layer on the top of the base electric current 3 as shown in FIG. 3 has been considered and prototyped.

As a method for manufacturing the entire vertical transistor having the structure shown in FIG. 3, a method using the steps shown in FIG. 4 (a3 to (e)) is known. First, as shown in FIG. 4(a), , 1st
The substrate having the second semi-coherent layer 2 with an epitaxial surface length on the semi-coherent layer 1 is patterned with resist 5 times, and then,
4. In the process shown in FIG. 4(b), a part of the second semi-integrated body layer 2 is etched completely vertically by dry etching using the resist 5 as a mask. Then, in the process shown in FIG. 4(c), Remove resist '6. Then, as shown in FIG. 4(d), the collector electrode 9 and the pace II electrode 3' (Il-Self-line) are formed, and then, as shown in FIG. 4(e), the emitter electrode 8 is completely formed on the back surface. It is something that forms.

Another method is the method shown in FIGS. 5(a) to 5(f). First, as shown in FIG. 5(a), a mask of resist 5 is formed on the surface of the first half-body layer on which the second half-24 body layer is formed, and this resist 5 is used as a mask as shown in FIG. As shown in (b), dry etching is performed to vertically process the second semi-integrated layer 2. Next, the fifth
1A (c) shows the damaged layer 6t caused by anisotropic wet etching: dry etching.
-Remove. Next, as shown in FIG. 5(d), the resist 5 is removed. After that, as shown in FIG. 5(e),
The collector electrode 9 and the base electrode 10 are diagonally deposited in a rainbow shape, and then an emitter electric image 8 is formed as shown in FIG.

[Problem that the invention seeks to solve]

In a vertical transistor, in order to control the current flowing in the vertical direction, the edge of the base electrode 10 can be safely brought into contact with the edge of the groove dug in this manufacturing method. It must be formed by vapor deposition. In order to vertically etch the grooves, dry etching is performed under highly anisotropic conditions, which results in the formation of a damaged layer 6 on the etched surface. I don't get it. Furthermore, if the damaged layer 6 is removed by wet etching, the perpendicularity deteriorates, making it necessary to use diagonal group N7Ft, which makes it difficult to control the base current width and thickness, and causes large variations in the 9% characteristics.

An object of the present invention is to eliminate deterioration of crystals accompanying the formation of a base electrode 10 in a method for manufacturing a vertical transistor;
The purpose is to provide a manufacturing method that improves the controllability of 100 million dimensions and allows mass production of high-performance vertical transistors.〇 [Problem 7! r: Means for Solving] In the method for manufacturing a vertical transistor/transistor of the present invention, a heat-resistant metal and an insulating film are laminated on a semiconductor layer, a part of the semiconductor layer is opened through etching, and the insulating film is A semiconductor layer is grown only in the opening using the mask as a mask, and a current control electrode and an active layer are formed, and the semiconductor layer is left open.

[For production]

As described above, the method for manufacturing a vertical transistor of the present invention includes laminating a heat-resistant metal and an insulating film on a semi-integrated layer, etching to open a portion of the film up to the semi-integrated layer, and then forming the insulating film. Is there a semiconductor layer only in the opening using a t mask? The heat-resistant metal is placed at the bottom and used as a current control electrode, and the grown semiconductor #9 is used as an active layer.

In this easy manufacturing method, first, the etching can be formed accurately according to the di-mask by reactive etching, and the second
Since a heat-resistant metal layer is formed on the semiconductor layer, the etching conditions can be easily selected and damage to the semiconductor layer is reduced, and the ef-damaged layer can be removed with a little wet etching thereafter. Therefore, if the dimensions of the current control electrode and the dimensions of the opening are kept accurate, it is possible to form an opening that does not cause damage to the semiconductor layer.

On the other hand, the growth of a semiconductor layer in an opening requires an insulating film on a heat-resistant metal, whereas in the conventional case where only a heat-resistant metal is used, poor quality crystals often grow on the upper layer. Since the method of the present invention has sufficient selectivity, a good semiconductor layer can be formed.

〔Example〕

Next, embodiments of the present invention will be described with reference to all the drawings. FIGS. 1(a) to 1(f) are cross-sectional views of an element in main steps shown in the order of steps to explain an embodiment of the present invention.

First, in the process shown in FIG. 1(a), a hydride VPE (Va
por Phase lli; pitaxy)
5 x 1016 cm" of n-Ga second semiconductor layer 2
A 200OA grown wafer is prepared, and the top surface is coated with heat-resistant Gold 3 by sputtering, and later with base T.
! A-type tungsten (W) of 30OA is applied to CVD Chemical Vapor Depos.
S i02 total 30 as insulating film 4
0OA stacking. Next, as shown in FIG. 19(b), a resist 5 is formed by X-ray exposure technology, and then as shown in FIG.
), using the resist 5 as a mask, 5 reactive ion etching is performed to completely form a grating with a spacing of 3000 A, W/SiO. Thereafter, as shown in Figure 1(d), the exposed and damaged GaAafi surface was etched with a 300A L diode using a wet etch, and then etched with hydride at a substrate temperature of 650°C as shown in Figure 1(e). To VPE! 5 x 10"cm-"tD
Selective growth is performed on an n-GaAs k 4000ASiO,i mask. Since 5i02 is used as a mask for selective growth, the selectivity is sufficient and a high quality n-GaAs layer can be grown.

Next, as shown in FIG. 1(f), an ohmic electrode is completely formed on the collector electrode part, and 3 layers of TiAu are added on top of the ohmic electrode.
μm is formed. And the entire collector electrode mask is 5i
After removing Ot'r and implanting protons, the collector is completely insulated and isolated except for the active layer below the polar surface. An emitter electrode is formed on the back surface. In the vertical transistor manufactured in this way, the dimensions of the base electrode can be precisely controlled, and! Since there is no damage caused by etching near the poles, vertical transistors with uneven T characteristics are suitable for mass production:
It can be manufactured easily.

〔Effect of the invention〕

As explained above, according to the present invention, in the manufacturing method of a vertical transistor, the dimensions of the base quadrupole can be controlled with high accuracy, an optimal design can be made, and there is no deterioration of the crystal near the polarization. Custom-made vertical transistors can be easily manufactured in mass production.

[Brief explanation of drawings]

11a(a) to 11(f) are cross-sectional views of constant elements shown in the order of steps to explain one embodiment of the present invention, and FIGS. 2 and 3 each show the structure and principle of a conventional vertical FFJT. Schematic cross-sectional views for explanation, No. 41 SiJ (a) to (e), and Fig. 5 (a)
) to (f) are all cross-sectional views of a companion element shown in step 110 for the purpose of fully explaining the conventional manufacturing method of a vertical FET. 1...First semiconductor layer, 2...Second semiconductor layer, 3...Heat-resistant metal (base as pole),
4... Insulating film, 5... Resist, 6...
...Damage layer due to dry etching, 7...
...Third semiconductor layer, 8...Emitter electrode, 9...Collector electrode, 10...Electron. 11...Single crystal. Tsumugi / Figure No. 7 No. 4 Figure Double Figure 4 Shoulder Left Figure No. T Mouth

Claims (1)

[Claims] A heat-resistant metal and an insulating film are laminated on the semiconductor layer, a part is opened to the semiconductor layer by etching, and the semiconductor layer is selectively grown only in the opening using the insulating film as a mask, and a current control electrode is formed. A method for manufacturing a vertical transistor, comprising forming an active layer.