JPS6224945B2 - - Google Patents
Info
- Publication number
- JPS6224945B2 JPS6224945B2 JP56158262A JP15826281A JPS6224945B2 JP S6224945 B2 JPS6224945 B2 JP S6224945B2 JP 56158262 A JP56158262 A JP 56158262A JP 15826281 A JP15826281 A JP 15826281A JP S6224945 B2 JPS6224945 B2 JP S6224945B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- oxygen
- region
- oxygen ions
- implantation step
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/023—Deep level dopants
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/919—Compensation doping
Landscapes
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Description
【発明の詳細な説明】
この発明は半導体の処理技術に関するものであ
り、特にシリコンに酸素をドープする技術に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor processing technology, and particularly to a technology for doping silicon with oxygen.
(本発明の背景技術)
集積回路製造技術における問題の1つはそこに
設けられている種々の半導体装置の幾つかのもの
或は全てのものを基体から絶縁することである。
基体から装置を絶縁するため現在使用されている
技術に拡散による絶縁がある。その方法では下方
領域と装置の形成部分を逆バイアスにすることに
よつて絶縁が達成される。また誘導体による絶縁
も使用され、その場合には誘電体絶縁層によつて
装置は基体から分離される。それらの技術は効果
的な絶縁を与えるものであるけれども、製造に多
くの時間を必要とし装置の製造価格を増加させる
欠点がある。BACKGROUND OF THE INVENTION One of the problems in integrated circuit manufacturing technology is isolating some or all of the various semiconductor devices thereon from a substrate.
A technique currently used to isolate devices from a substrate is diffusion isolation. In that method, isolation is achieved by reverse biasing the underlying region and the forming portion of the device. Dielectric insulation is also used, in which a dielectric insulation layer separates the device from the substrate. Although these techniques provide effective isolation, they have the disadvantage of requiring significant manufacturing time and increasing the manufacturing cost of the device.
最近イオン注入(ionimplantation)技術を利
用した絶縁技術が開発された。その技術では半導
体基体中の1つの層が酸素で多量にイオン注入さ
れる。基体は次いで高温に加熱され、シリカの基
体層が形成される。この処理は長時間のイオン注
入を必要とし、結晶の損傷が著しいために比較的
高温で長時間焼鈍する必要がある
(この発明の概要)
したがつて、この発明の一般的な目的は上記の
ような従来技術の欠点を除去することである。 Recently, insulation technology using ion implantation technology has been developed. In that technique, a layer in a semiconductor body is heavily implanted with oxygen. The substrate is then heated to an elevated temperature to form a silica substrate layer. This process requires ion implantation for a long period of time, and requires annealing at a relatively high temperature for a long period of time due to significant damage to the crystal. The purpose is to eliminate the drawbacks of the prior art.
さらに言えば、この発明の目的はp型基体中に
絶縁領域を形成するための、この種の通常の方法
の有する欠点を有しない方法を開発することであ
る。 Furthermore, it is an object of the invention to develop a method for forming insulating regions in p-type substrates which does not have the disadvantages of conventional methods of this type.
この発明の別の目的は比較的廉価でしかもすぐ
れた結果を達成することのできるこの種の形式の
方法を提供することである。 Another object of the invention is to provide a method of this type which is relatively inexpensive and yet allows excellent results to be achieved.
この発明の付随的な目的は改善された絶縁層ま
たは領域を有する半導体装置を提供することにあ
る。 A secondary object of the invention is to provide a semiconductor device having an improved insulating layer or region.
これらの目的および以下の説明から明らかにな
ると思われるとその他の目的を達成するために、
この発明の特徴とする少なくとも1個の半導体装
置を基体の残部から絶縁するためにp型シリコン
基体中に絶縁領域を形成する方法は、所望領域に
おける基体材料のドープレベルに実質上対応する
濃度レベルまでその所望領域に酸素イオンをイオ
ン注入する工程と、酸素イオンが少なくとも前記
所望領域中のp型ドープ不純物の効果を補償して
その領域を真性からn導電型の範囲のシリコン絶
縁領域に変換する如く酸素イオンを活性化するの
に充分な温度に基体を加熱する工程とより成つて
いる。 In order to achieve these purposes and such other purposes as may become apparent from the description below.
A method of forming an insulating region in a p-type silicon substrate for isolating at least one semiconductor device from the remainder of the substrate features a doping level substantially corresponding to the doping level of the substrate material in the desired region. implanting oxygen ions into the desired region until the oxygen ions at least compensate for the effects of p-type doped impurities in the desired region, converting the region into a silicon insulating region ranging from intrinsic to n conductivity type; heating the substrate to a temperature sufficient to activate the oxygen ions.
この発明の別の観点によれば活性表面を有する
p型シリコン基体と、その活性表面に配置された
少なくとも1個の半導体装置と、半導体装置と基
体の残部との間に設けられた真性からn導電型ま
での範囲の酸素を含むシリコン絶縁領域とより成
る半導体構造が提供される。 According to another aspect of the invention, a p-type silicon substrate having an active surface, at least one semiconductor device disposed on the active surface, and an intrinsic silicon substrate disposed between the semiconductor device and the remainder of the substrate. A semiconductor structure is provided comprising a silicon insulating region containing oxygen of up to a range of conductivity types.
酸素のリツチなシリコンは例えば430乃至470℃
の温度に加熱された時、強いドナー活性を示す。
この効果の本質は充分に理解されていない。しか
しSiO4錯化合物の形成が処理中の何等かの部分
で働くものと考えられている。より低い温度の加
熱では錯化合物は形成されず、したがつてドナー
は発生しない。一方もつと高い温度に加熱しても
ドナーは発生しない。酸素のリツチなp型シリコ
ンは長時間加熱が続けられれば導電型がn型に変
化する。この導電型の反転する前に酸素錯化合物
ドナーがもとのp型材料中に存在するアクセプタ
を補償して半導体の比抵抗を増加させる結果真性
シリコンが形成される。 Oxygen-rich silicon, for example, has a temperature of 430 to 470°C.
It exhibits strong donor activity when heated to a temperature of .
The nature of this effect is not fully understood. However, it is believed that the formation of SiO 4 complex compounds occurs at some point during the processing. At lower heating temperatures no complexes are formed and therefore no donors are generated. On the other hand, no donor is generated even if heated to a high temperature. If oxygen-rich p-type silicon is heated for a long time, its conductivity type changes to n-type. Before this conductivity type inversion, the oxygen complex donor compensates for the acceptor present in the original p-type material and increases the resistivity of the semiconductor, resulting in the formation of intrinsic silicon.
(実施例の説明)
上述の、およびその他のこの発明の目的ならび
に特徴は添付図面を参照にした以下の説明により
一層明瞭になるであろう。(Description of Embodiments) The above-mentioned and other objects and features of the present invention will become clearer from the following description with reference to the accompanying drawings.
図面を参照すると、例えばバイポーラ或は
MOSトランジスタのような半導体装置11はシ
リコン基体の活性表面に形成されている。半導体
装置の形成に先立つて、酸素のリツチな層13が
酸素イオンの軽いイオン注入によつて基体中に形
成される。典型的には層13は1018cm-3の酸素レ
ベルにイオン注入される。次いで標準的な技術に
よつて基体表面に半導体装置11が形成され、そ
れに続いて基体は430℃乃至470℃、好ましくは
450℃に加熱されシリコンと酸素の複合体を活性
化させ、もとのp型シリコン中に存在しているp
型ドープ不純物の効果を補償或は過補償して層1
3中に高比抵抗またはn型の領域を形成し、半導
体装置11を基体12から絶縁する。 Referring to the drawings, for example bipolar or
A semiconductor device 11, such as a MOS transistor, is formed on the active surface of a silicon substrate. Prior to the formation of the semiconductor device, an oxygen-rich layer 13 is formed in the substrate by light implantation of oxygen ions. Typically layer 13 is implanted to an oxygen level of 10 18 cm -3 . A semiconductor device 11 is then formed on the surface of the substrate by standard techniques, and the substrate is subsequently heated to 430°C to 470°C, preferably
It is heated to 450℃ to activate the silicon-oxygen complex, which removes the p-type silicon present in the original p-type silicon.
layer 1 by compensating or overcompensating for the effect of type doping impurities.
A high resistivity or n-type region is formed in the substrate 3 to insulate the semiconductor device 11 from the substrate 12 .
この技術は基体から半導体装置を絶縁すること
が要求される場合にMOSまたはバイポーラ処理
に使用することができる。酸素を含まないp型シ
リコンウエハは半導体装置構造の最も深い位置を
越えた深さまで酸素をイオン注入される。それか
ら半導体装置が普通の方法で形成され、その後で
装置の金属化処理に先立つてウエハは不活性雰囲
気中で430〜470℃に加熱されて活性化され、絶縁
層とされる。最後にウエハに金属化処理が行なわ
れ、切断され、容器にパツクされて最終の半導体
装置が形成される。 This technique can be used in MOS or bipolar processing when it is required to isolate the semiconductor device from the substrate. Oxygen-free p-type silicon wafers are implanted with oxygen to a depth beyond the deepest point of the semiconductor device structure. Semiconductor devices are then formed in a conventional manner, after which the wafer is activated by heating to 430 DEG -470 DEG C. in an inert atmosphere to provide an insulating layer prior to device metallization. Finally, the wafers are metallized, cut, and packaged into containers to form the final semiconductor devices.
ここに説明した技術はDMOS(二重拡散
MOS)構造の製造に特に適している。それはそ
のような構造ではp型基体上の軽いドープのn型
領域が必要であるからである。通常そのような構
造は基体上に高温でエピタキシヤル層を成長させ
ることによつて実現している。しかしながらその
ような高温の使用はウエハの歪みや層の厚さの制
御の関連した問題を包蔵している。この発明の技
術は比較的低い温度を使用することによつて実質
上これらの問題を解決している。 The technology described here is DMOS (double diffused
Particularly suitable for manufacturing MOS) structures. This is because such a structure requires a lightly doped n-type region on a p-type substrate. Typically such structures are achieved by growing epitaxial layers on a substrate at high temperatures. However, the use of such high temperatures involves associated problems of wafer distortion and layer thickness control. The technique of the present invention substantially solves these problems by using relatively low temperatures.
例えば、もしも酸素イオンがp型浮遊領域基体
(酸素を含有せず)中にイオン注入され、続いて
焼鈍されるならば酸素ドナは半導体表面の導電型
を反転させ、n型層が形成される。この層の比抵
抗は焼鈍期間の対応する調節によつて制御でき
る。さらに、もしも酸素イオンが計画された活性
領域にマスクを通して注入されるならば、その場
合には同時に横方向の絶縁も達成される。これは
普通の拡散/駆動処理の必要を無くすものであ
る。 For example, if oxygen ions are implanted into a p-type floating region substrate (containing no oxygen) and subsequently annealed, the oxygen donor reverses the conductivity type of the semiconductor surface and an n-type layer is formed. . The resistivity of this layer can be controlled by a corresponding adjustment of the annealing period. Furthermore, if oxygen ions are implanted through a mask into the planned active region, then lateral isolation is also achieved at the same time. This eliminates the need for conventional diffusion/driving processes.
第2図は代表的なDMOS構造を示している。こ
の構造はここに説明した酸素イオン注入技術を使
用して製造することができる。装置は酸素を含ま
ないp型基体中に形成することができる。図示の
ように装置は通常のソースS、ゲートG、および
ドレインDの各領域を有しており、n-領域によ
つて基体から絶縁されている。n-領域は典型的
なものでは深さが1μmで、酸素のイオン注入に
続いて430〜470℃の温度で焼鈍して酸素ドナー中
心を活性化することによつて形成される。代表的
なものではそのような層はビーム強度5×1013cm
-2、200KeVのエネルギの2重電荷酸素イオンの
注入によつて得ることができ、それによつて1μ
mの深さに酸素ピーク濃度1013cm-3が与えられ、
次いで450℃で1000分間焼鈍される。酸素イオン
のエネルギおよび濃度はもちろん所望されるn型
層のドープレベルに応じて選択され、焼鈍時間は
最適のドナ濃度が得られるように選択される。 Figure 2 shows a typical DMOS structure. This structure can be fabricated using the oxygen ion implantation techniques described herein. The device can be formed in an oxygen-free p-type substrate. As shown, the device has the usual source S, gate G, and drain D regions, isolated from the substrate by an n - region. The n - region is typically 1 μm deep and is formed by ion implantation of oxygen followed by annealing at a temperature of 430-470° C. to activate the oxygen donor centers. Typically such a layer has a beam intensity of 5 x 10 13 cm
-2 , can be obtained by implantation of doubly charged oxygen ions with an energy of 200 KeV, whereby 1 μ
An oxygen peak concentration of 10 13 cm -3 is given at a depth of m,
It is then annealed at 450°C for 1000 minutes. The oxygen ion energy and concentration are of course selected depending on the desired n-type layer doping level, and the annealing time is selected to obtain the optimum donor concentration.
上述したこの発明の技術は明らかにデイスクリ
ートな装置の製造に限定されるものではなく、も
ちろん集積回路の製造にも効果的に適用すること
ができる。 The inventive technique described above is clearly not limited to the manufacture of discrete devices, but can of course also be effectively applied to the manufacture of integrated circuits.
以上この発明の原理を特定の装置に関連して説
明したが、これは単なる例示に過ぎないものであ
つて、特許請求の範囲に記載したこの発明の技術
的範囲を制限するものではないことを明言する。 Although the principle of this invention has been explained above in relation to a specific device, it should be understood that this is merely an example and does not limit the technical scope of this invention as set forth in the claims. Make a clear statement.
第1図はシリコン基体中に形成され、基体から
高比抵抗層によつて絶縁された半導体装置の断面
図であり、第2図は酸素イオン注入層によつて絶
縁されたDMOS構造の断面図である。
11…半導体装置、12…基体、13…酸素イ
オン注入層、S…ソース、D…ドレイン、G…ゲ
ート。
FIG. 1 is a cross-sectional view of a semiconductor device formed in a silicon substrate and insulated from the substrate by a high resistivity layer, and FIG. 2 is a cross-sectional view of a DMOS structure insulated by an oxygen ion implantation layer. It is. DESCRIPTION OF SYMBOLS 11... Semiconductor device, 12... Base, 13... Oxygen ion implantation layer, S... Source, D... Drain, G... Gate.
Claims (1)
活性表面に配置された少なくとも1個の半導体装
置と、該半導体装置と前記基体の残りの部分との
間に設けられた酸素をドープ不純物として含む真
性からn導電型までの範囲のシリコンの絶縁領域
とより成る半導体構造。 2 前記半導体装置がDMOS形態を有している特
許請求の範囲第1項記載の半導体構造。 3 前記絶縁領域が前記活性表面から1μmの深
さに延在している特許請求の範囲第1項記載の半
導体構造。 4 前記絶縁領域が酸素イオンを注入し、酸素イ
オンが活性化して絶縁領域中のドープ不純物の効
果を補償する温度に基体を加熱することによつて
生じたものである特許請求の範囲第1項記載の半
導体構造。 5 基体材料のドープレベルに実質上対応する濃
度レベルで前記基体の所望領域に層状に酸素イオ
ンを注入する工程と、 前記層状に酸素イオンを注入した領域を真性か
らn導電型までのレベルを有する層状の分離領域
に変換するのに充分の時間に亙つて前記基体を約
430℃乃至約470℃の範囲の温度に加熱する工程と
を具備することを特徴とするp型にドープされた
シリコン基体中に真性またはn導電型の導電的に
分離する領域を形成した半導体構造の形成方法。 6 前記イオン注入工程の少なくとも一部の期間
に基体の選択された区域をマスクする工程を有し
ている特許請求の範囲第5項記載の方法。 7 前記イオン注入工程の行なわれる前には実質
上酸素を含有していない基体が使用される特許請
求の範囲第5項記載の方法。 8 前記注入工程において200KeVのエネルギの
酸素イオンによつて基体を衝撃して1μmの深さ
に1018cm-3のピーク酸素濃度を与える特許請求の
範囲第5項記載の方法。 9 基体のドープレベルに実質上対応する濃度レ
ベルでp型にドープされたシリコン基体中に層状
に酸素イオンを注入する工程と、 前記基体中に1以上の半導体装置を形成する工
程と、 その後に、前記層状に酸素イオンを注入した領
域を真性またはn導電型の領域に変換して前記1
以上の半導体装置を分離するために前記層状に酸
素イオンを注入した領域中の酸素を活性化して少
なくともこの層状領域中のp型不純物の効果を補
償するように前記基体を約430℃乃至約470℃の範
囲の温度に加熱する工程とを具備することを特徴
とする半導体構造の形成方法。 10 前記イオン注入工程の少なくとも一部の期
間に基体の選択された区域をマスクする工程を有
している特許請求の範囲第9項記載の方法。 11 前記イオン注入工程の行なわれる前には実
質上酸素を含有していない基体が使用される特許
請求の範囲第9項記載の方法。 12 前記注入工程において200KeVのエネルギ
の酸素イオンによつて基体を衝撃して1μmの深
さに1018cm-3のピーク酸素濃度を与える特許請求
の範囲第9項記載の方法。[Scope of Claims] 1. A p-type silicon substrate having an active surface, at least one semiconductor device disposed on the active surface, and an oxygen disposed between the semiconductor device and the remainder of the substrate. A semiconductor structure consisting of an insulating region of silicon ranging from intrinsic to n conductivity type containing as a doped impurity. 2. The semiconductor structure according to claim 1, wherein the semiconductor device has a DMOS configuration. 3. The semiconductor structure of claim 1, wherein the insulating region extends to a depth of 1 μm from the active surface. 4. The insulating region is produced by implanting oxygen ions and heating the substrate to a temperature at which the oxygen ions become activated and compensate for the effects of doped impurities in the insulating region. The semiconductor structure described. 5. implanting oxygen ions in a layered manner into a desired region of the substrate at a concentration level substantially corresponding to the doping level of the substrate material; The substrate is heated for a period of time sufficient to convert it into layered separated regions.
heating to a temperature in the range of 430°C to about 470°C. How to form. 6. The method of claim 5, further comprising the step of masking selected areas of the substrate during at least a portion of the ion implantation step. 7. The method of claim 5, wherein a substantially oxygen-free substrate is used before said ion implantation step is performed. 8. The method of claim 5, wherein the implantation step bombards the substrate with oxygen ions at an energy of 200 KeV to provide a peak oxygen concentration of 10 18 cm -3 at a depth of 1 μm. 9. implanting oxygen ions in a layer into a p-doped silicon substrate at a concentration level substantially corresponding to the doping level of the substrate; forming one or more semiconductor devices in said substrate; , converting the layered region into which oxygen ions are implanted into an intrinsic or n-conductivity type region;
In order to separate the above-described semiconductor devices, the substrate is heated at a temperature of about 430° C. to about 470° C. so as to activate oxygen in the region into which oxygen ions are implanted into the layered region and compensate for at least the effect of the p-type impurity in this layered region. A method for forming a semiconductor structure, comprising the step of heating to a temperature in the range of .degree. 10. The method of claim 9, further comprising the step of masking selected areas of the substrate during at least a portion of the ion implantation step. 11. The method of claim 9, wherein a substantially oxygen-free substrate is used before said ion implantation step is performed. 12. The method of claim 9, wherein said implantation step bombards the substrate with oxygen ions at an energy of 200 KeV to provide a peak oxygen concentration of 10 18 cm -3 at a depth of 1 μm.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8032246A GB2085224B (en) | 1980-10-07 | 1980-10-07 | Isolating sc device using oxygen duping |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57132340A JPS57132340A (en) | 1982-08-16 |
| JPS6224945B2 true JPS6224945B2 (en) | 1987-05-30 |
Family
ID=10516517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56158262A Granted JPS57132340A (en) | 1980-10-07 | 1981-10-06 | Semiconductor structure and method of producing same |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4490182A (en) |
| JP (1) | JPS57132340A (en) |
| DE (1) | DE3138140A1 (en) |
| FR (1) | FR2491679B1 (en) |
| GB (1) | GB2085224B (en) |
| IE (1) | IE52184B1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6031232A (en) * | 1983-07-29 | 1985-02-18 | Toshiba Corp | Manufacture of semiconductor substrate |
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| USH569H (en) | 1984-09-28 | 1989-01-03 | Motorola Inc. | Charge storage depletion region discharge protection |
| EP0197948A4 (en) * | 1984-09-28 | 1988-01-07 | Motorola Inc | PROTECTION AGAINST DISCHARGE OF A DEPOSIT ZONE OF A LOAD STORAGE. |
| JPS61121433A (en) * | 1984-11-19 | 1986-06-09 | Sharp Corp | Semiconductor substrate |
| US4706378A (en) * | 1985-01-30 | 1987-11-17 | Texas Instruments Incorporated | Method of making vertical bipolar transistor having base above buried nitride dielectric formed by deep implantation |
| US4717677A (en) * | 1985-08-19 | 1988-01-05 | Motorola Inc. | Fabricating a semiconductor device with buried oxide |
| US4676841A (en) * | 1985-09-27 | 1987-06-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C. |
| GB2183905B (en) * | 1985-11-18 | 1989-10-04 | Plessey Co Plc | Method of semiconductor device manufacture |
| US4682407A (en) * | 1986-01-21 | 1987-07-28 | Motorola, Inc. | Means and method for stabilizing polycrystalline semiconductor layers |
| JPS62219636A (en) * | 1986-03-20 | 1987-09-26 | Hitachi Ltd | Semiconductor device |
| JPH0738435B2 (en) * | 1986-06-13 | 1995-04-26 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| US4863878A (en) * | 1987-04-06 | 1989-09-05 | Texas Instruments Incorporated | Method of making silicon on insalator material using oxygen implantation |
| US4849370A (en) * | 1987-12-21 | 1989-07-18 | Texas Instruments Incorporated | Anodizable strain layer for SOI semiconductor structures |
| US5670387A (en) * | 1995-01-03 | 1997-09-23 | Motorola, Inc. | Process for forming semiconductor-on-insulator device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3622382A (en) * | 1969-05-05 | 1971-11-23 | Ibm | Semiconductor isolation structure and method of producing |
| US3666548A (en) * | 1970-01-06 | 1972-05-30 | Ibm | Monocrystalline semiconductor body having dielectrically isolated regions and method of forming |
| GB1334520A (en) * | 1970-06-12 | 1973-10-17 | Atomic Energy Authority Uk | Formation of electrically insulating layers in semiconducting materials |
| US3897274A (en) * | 1971-06-01 | 1975-07-29 | Texas Instruments Inc | Method of fabricating dielectrically isolated semiconductor structures |
| US3976511A (en) * | 1975-06-30 | 1976-08-24 | Ibm Corporation | Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment |
| JPS5721856B2 (en) * | 1977-11-28 | 1982-05-10 | Nippon Telegraph & Telephone | Semiconductor and its manufacture |
| JPS5640269A (en) * | 1979-09-11 | 1981-04-16 | Toshiba Corp | Preparation of semiconductor device |
-
1980
- 1980-10-07 GB GB8032246A patent/GB2085224B/en not_active Expired
-
1981
- 1981-09-14 US US06/301,794 patent/US4490182A/en not_active Expired - Fee Related
- 1981-09-25 DE DE19813138140 patent/DE3138140A1/en active Granted
- 1981-10-06 JP JP56158262A patent/JPS57132340A/en active Granted
- 1981-10-06 IE IE2339/81A patent/IE52184B1/en unknown
- 1981-10-07 FR FR8118851A patent/FR2491679B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2491679A1 (en) | 1982-04-09 |
| DE3138140C2 (en) | 1989-10-19 |
| IE812339L (en) | 1982-04-07 |
| GB2085224A (en) | 1982-04-21 |
| JPS57132340A (en) | 1982-08-16 |
| IE52184B1 (en) | 1987-08-05 |
| FR2491679B1 (en) | 1988-03-04 |
| DE3138140A1 (en) | 1982-05-19 |
| GB2085224B (en) | 1984-08-15 |
| US4490182A (en) | 1984-12-25 |
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