JPS62292020A - Peak value follow up circuit - Google Patents

Abstract

PURPOSE:To prevent holding performance from being lowered, by latching a peak value, and controlling the peak value so as to be held during a period until to the next peak point. CONSTITUTION:As for the code bit of an A/D converter 1, by passing a signal delayed by the cycle of a clock T1 at a latch 6, and the signal inverted at an inverter 4, through a NOR gate 7, a pulse equivalent to the cycle of the clock T1 is generated only at the time of changing the code of an input signal from a positive to a negative, and a clock T2 is added on a latch 9 through an AND gate 8, and the peak value of the input signal at a time t5 is written. Simultaneously, a latch 2 is reset. The code bit is inputted to an AND gate 5 through the inverter 4, and no change occurs in the latch 2 for peak detection in the negative period of the input signal. The latch 2 performs the tracking of the maximum value from a time t1a, and holds the value at a time t16 when the input signal starts to drop, and transfers the held value to the latch 9 at a time t17 when the code of the input signal changes from the positive to the negative, and resets the latch 2 simultaneously. Thus, by repeating such operation, the output of the latch 9 in which a positive peak value by every cycle is followed up, can be obtained.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a peak value tracking circuit for digitized signals, and in particular to a circuit for accurately tracking changes in the peak value of an AC component. This invention relates to a digital peak value tracking circuit that can track peak values.

[Conventional technology]

Figure 3 shows a conventional analog peak value hold circuit.
In the figure, 11 is an operational amplifier, and this operational amplifier 1
A series circuit consisting of a diode 12 and a capacitor 13 is connected to the output terminal of the operational amplifier 1, and a connection point between the diode 12 and the capacitor 13 is connected to the negative input terminal of the operational amplifier 11.

In the conventional peak value tracking circuit having such a configuration, when an AC signal is input to the input terminal (+) of the operational amplifier 11, during the rising process of the AC signal, the input signal is increased through the diode 12 up to the maximum peak value. Although the capacitor 13 is charged to have the same potential as the level, the output of the operational amplifier 11 decreases during the process of decreasing the AC signal. However, the potential across the capacitor 13 is not discharged due to the action of the diode 12 that prevents reverse flow, and thus maintains its maximum peak value.

[Problem that the invention seeks to solve]

Conventional peak value tracking circuits are configured as described above, so they can easily maintain peak values at relatively high levels. requires a discharge circuit with a required time constant, and if the time constant is set to a large value, the follow-up characteristics for the AC signal will deteriorate, while if the time constant is set to a small value, the hold performance will deteriorate. there were.

This invention was made in order to solve the above-mentioned problems, and it is possible to accurately maintain the value of the peak point of the AC signal until the next peak point, and to follow the peak value of the AC signal to obtain stable operation. The purpose is to obtain a circuit.

[Means for solving problems]

The peak value tracking circuit according to the present invention detects and latches a peak value from a numerical value obtained by sampling and quantizing an alternating current signal into a digital signal, and uses the peak value detection means 100 to detect and latch the peak value, and transfers the latched peak value to the next peak point. The control means 200 causes the peak value holding means 9 to hold the peak value for a period of
It was controlled by

[Effect]

In the peak value tracking circuit according to the present invention, the peak value detection means 100 holds the peak value immediately before the input signal falls, and the time interval control means 200 detects the peak value when the sign of the input signal changes from positive to negative. Since the peak value holding means 9 is latched and the peak value of the peak value detecting means 100 is controlled to be reset, changes in the peak value can be avoided! [Can be followed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an A/D converter (A/D conversion means) that samples and quantizes an analog input signal using a clock T1 and outputs a signed binary number. 2 is a latch that temporarily stores the past maximum value, 3 is the first human input as the output of A/D converter 1, the second input as the output of latch 2, and the first input as the second input. The latch 2 and the comparator 3 constitute a peak value detecting means 100, which is a comparator that outputs logic 1 when they are greater than or equal to each other. The A/D converter 1 and the peak value detection means 100 are controlled by the control means 200. 4 is an inverter which inputs the sign bit output of the A/D converter 1 manually; 5, the first input is the output of the inverter 4, and the second input is the clock T2. A that takes the third input as the output of comparator 3 and outputs it to the clock input of latch 2.
ND gate, 6 is a latch that delays the sign bit output of A/D converter 1 by the period of clock T1, 7 is the first input as the output of inverter 4, and the second input as the output of latch 6 NOR gate 8 is an AN whose first input is the output of NOR gate 7 and whose second input is clock T2.
This is the D gate.

9 takes the output of latch 2 as input, and ANDs the clock input.
This is a latch (peak value holding means) for NO gate output. Note that the output of the AND gate 8 is also connected to the reset input of the latch 2.

Regarding the peak value tracking circuit of the present invention having the above configuration, FIG.
This will be explained with reference to the drawings. In the figure, waveform (a) is an analog human input signal applied to the input of A/D converter 1, and waveform r
b) and (C) are two-phase blackfish T1 and T2. A/D
Converter 1 samples the input signal (a'l,
and quantization to convert it into a signed binary number. 3(d) shows how the output data of the A/D converter 1 changes, and FIG. 2(e) shows its sign bit. Note that the sign bit is represented by negative logic, and is logic 0 when it is a positive value, and logic 1 when it is a negative value.

Now, in FIG. 2, if the latch 2 is reset to the value 0 at time t1, the output of the comparator 3 becomes logic 1 because the output value of the A/D converter 1 is a dog. Further A/
Since the sign bit of D converter 1 is logic O, clock T2 is applied to latch 2 through AND gate 5, and this latch 2 is updated to the output value of A/D converter 1 at time tI. At time t2, the output value of A/D converter 1 further increases, so the value of latch 2 is updated. Similarly, the value of latch 2 is updated one after another until time tr when the input signal increases. At time tg, the input signal of comparator 3 decreases, so its output becomes logic 0, and AND gate 5 inhibits clock T2 to latch 2, so latch 2 retains the peak value updated at time 11. do. Since the output of the comparator 3 is a logic 0 until time t when the input signal continues to decrease, the latch 2 holds the peak value at time t5. On the other hand, the sign bit of A/D converter 1 is set to latch 6.
The signal delayed by the period of clock T1 and inverter 4
By passing the inverted signal through the NOR gate 7, a pulse equal to the period of the clock T1 is generated as shown in FIG. 2(f) only when the sign of the input signal changes from positive to negative. When there is an output pulse of 7, the clock T2 is applied to the latch 9 through the ANDNO gate, and the peak value of the input signal at time ty is written. At the same time, latch 2 is reset to enable tracking of the next peak value. Here, since the sign bit is input to the AND gate 5 through the inverter 4, the latch 2 for peak detection does not change during the period when the input signal is negative. Time ta
3, latch 2 tracks the maximum value, holds the value at time t+'7 when the human input signal begins to decrease, and transfers the held value to latch 9 at time t+'7 when the sign of the input signal changes from positive to negative, At the same time, latch 2 is reset. By repeating the above operations, a value that follows the positive peak value appears in the output of the latch 9 every cycle of the input signal.

In the above embodiment, the analog input signal is sampled, quantized, and latched by the A/D converter 1, but a switched capacitor is used instead of this launch, and the analog input signal is Instead, a comparator may be used to determine whether the input signal is positive or negative, and the same effect as in the above embodiment can be achieved. - [Effects of the Invention] As described above, according to the present invention, the peak value in the digital signal of the sampled and quantized AC signal is launched, and the latched peak value is used as the period until the next peak point. Since the configuration is controlled to hold, there is no problem that the response speed and tracking characteristics of the time constant circuit conflict with each other, and the effect is that a highly reliable peak value tracking circuit that operates stably and accurately can be obtained. .

[Brief Description of the Drawings] Fig. 1 is a configuration diagram showing a peak value tracking circuit according to an embodiment of the present invention, Fig. 2 is a waveform diagram for explaining the present invention in detail, and Fig. 3 is a conventional AC FIG. 2 is a configuration diagram showing a signal peak value tracking circuit. 1... A/D converter (A/D conversion means), 2... Latch, 3... Comparator, 4... Inverter, 5...
3 person AND gate, 6...lunch, 7...NO
R gate, 8... 2-person AND gate, 9... Latch (peak value holding means), 11... Operational amplifier, 1
2...Diode, 13...Capacitor, 100...
. . . Peak value detection means, 200 . . . Control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Attorney Masu Oiwa, Atsushi Oiwa (2 people) Atsushi 3rd figure procedural amendment (self-motivated 2nd day of Showa 1962, 62 4 5.', Director General of the Japan Patent Office)
-〆1, Indication of the incident Patent application Sho 6□-136748
No. 2, Name of the invention Peak value tracking circuit 3, Relationship with the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, agent address 5, Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo, ili Tadashi Column for detailed explanation of the subject invention. 6. Contents of correction (1) In the 15th line of page 6 of Akira IIIw, the phrase ``represented by negative logic'' is corrected to ``according to two's complement representation.'' (2) In the same book, page 7, line 12, replace rtJ with “t9”
and correct it. that's all

Claims (1)

[Claims] A peak value detection means for sequentially inputting a sampled and quantized digital signal of an input analog signal and detecting and latching the peak value of the analog signal by comparing the magnitude thereof; Peak value holding means holds and outputs the latched peak value for a period from the peak point of the analog signal to the next peak point, and the sign bit of the digital signal is positive and the magnitude comparison in the peak value detection means is When the result is large, the digital signal is latched by the peak value detection means, and at the time when the sign bit changes from positive to negative, the peak value latched by the peak value detection means is held as the peak value. 1. A peak value tracking circuit comprising control means for transmitting and holding the peak value to the peak value detection means and for controlling the peak value detection means to be reset.