JPS6246384Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a television receiver, particularly when image information transmitted as a digital signal multiplexed during the vertical retrace period of a standard television broadcast signal is stored in the memory device of the television receiver. , relates to a screen erasing circuit that erases this image information.

BACKGROUND ART A system for transmitting image information such as text and graphics using television broadcast radio waves is generally called television text multiplex broadcasting. This teletext broadcasting is usually transmitted while being superimposed on the vertical blanking period of the video signal. Therefore, one entire screen of image information cannot be transmitted within one image scanning period (in the case of interlaced scanning, one frame period, hereinafter referred to as one field period) in which the video signal forms one screen. In this way, the image information transmitted in one field is limited to one part of one screen, so the transmitted image information is stored sequentially and is displayed as a video only after one screen is formed. The structure is taken. By the way, the image information to be transmitted is not always the same, so if image information to be transmitted later overlaps the image information in the storage device, the screen on the cathode ray tube will look confused. Therefore, in order to erase the previous image information, a screen erase instruction signal is transmitted using the vertical retrace period in the same way as the image information. This signal is decoded by the central processing unit (hereinafter abbreviated as CPU) within the receiver, and the CPU outputs a screen erase signal.

By the way, in order to erase all the image information in the storage device, it is necessary to scan the entire screen, and therefore, the screen erasure scanning time is required to be equivalent to one field period.

However, since the screen erasing instruction signal is decoded by software, the time of the screen erasing signal is not constant.
Generally, the time is shorter than the time of one feed.

This point will be explained below.

As mentioned above, the screen erase instruction signal is terminated according to a predetermined program for ease of decoding.
This is done by software in the CPU, and after the decoding is completed, a screen erase signal is output. On the other hand, the output state is terminated by the vertical synchronization signal output from the synchronization separation circuit of the receiver, that is, by hardware.

This situation is illustrated in Figure 1. A is a waveform diagram of the vertical synchronization pulse output from the synchronization separation circuit, B is a screen erase signal when decoding takes a relatively long time, and C is a screen erase signal when decoded in a shorter time. . In the figure, the screen erase instruction signal is included within the vertical retrace period at the left end of waveform A.

As described above, the conventional erasing circuit was unable to generate an erasing signal of sufficient time to erase one screen of image information.

DISCLOSURE OF THE INVENTION It is an object of the present invention to decode the screen erase instruction signal during the vertical retrace period using software means, that is, to cause the CPU to decode the signal according to a predetermined program, while still erasing the image information of one screen. It is an object of the present invention to provide a screen erasing circuit that generates a sufficient screen erasing signal.

This invention consists of a CPU that decodes the transmitted screen erase instruction signal using the vertical retrace period of the video signal and outputs a detection signal pulse, and a CPU that uses this detection signal pulse as a clock and inputs a predetermined level state as data. The vertical synchronization signal pulse output from the first flip-flop circuit (hereinafter the flip-flop circuit will be abbreviated as FF) and the synchronization separation circuit of the receiver is used as the clock, and the first flip-flop circuit
A second FF that uses the output information as data input and outputs it as a screen erase signal, and a vertical synchronization signal that is output next to the inverted output of the second FF and the vertical synchronization signal pulse that operated the second FF. A pulse is taken as two inputs, and a pulse whose pulse width is the time when these input level states match is output to clear the first FF and the second FF, and the second FF is cleared.
It is constituted by a gate circuit that makes the pulse width of the screen erase signal output by the FF equal to the period of one field.

An advantage of the invention is that the circuit construction is simple and therefore also inexpensive.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be explained below with reference to the drawings.

FIG. 2 is a circuit diagram according to an embodiment of the present invention,
1 and 2 are D-FF, and 3 is a 2-input OR gate circuit. The data input terminal of FF1 is connected to the power supply V _DD via a resistor R, and the clock input terminal is connected to an output terminal of a screen erase instruction detection signal of a CPU (central processing unit) in the receiver (not shown). There is. The data input terminal of FF2 is connected to the Q output terminal of FF1, and the clock input terminal is connected to the output terminal of a synchronous separation circuit in a receiver (not shown). Next, one of the two input terminals of the two-input OR circuit 3 is connected to the output terminal of the FF2, and the remaining one is connected to the output terminal of the synchronous separation circuit. Also, the output terminals of the 2-input OR circuit are FF1 and FF2.
is connected to the clear input terminal of

Next, the operation of the circuit according to the present invention will be explained, but for the sake of clarity, a timing chart of waveforms of each terminal shown in FIG. 3 will be used. In the figure,
Waveform A is a vertical synchronization signal output from the synchronization separation circuit, and its one pulse width is equal to the period of one video signal. Waveform B is obtained after decoding the screen erase instruction signal sent using the vertical retrace period of the video signal.
This is a detection signal pulse output from the CPU. Waveform C is the Q output signal of FF1, so also
This is the data input signal of FF2. Waveform D is FF
2, and waveform E is the output signal of the gate circuit 3. Waveform 5 is the output signal of FF2, which is a required signal of the present invention.

Assume now that as an initial state, waveforms C and H are at "L" level and waveform E is at "H" level. Vertical synchronization signal pulse (waveform A) is output from the synchronization separation circuit.
Although it is input to the clock input terminal of FF2, since the data input is at the "L" level (waveform C), there is no change in the output state. However, the CPU decodes the screen erase instruction signal sent using the vertical retrace period of the video signal, and the detection pulse (waveform B)
When input to the clock input terminal of FF1, the FF
1 reads the data input "H" level and outputs "H" level from the Q output. Then, the vertical synchronization signal pulse (waveform A) is output from the synchronization separation circuit.
When input to the clock input terminal of FF2, F.
F.2 reads the data input "H" level (waveform C) and outputs "H" level from the Q output (waveform B) and "L" level from the output (waveform D). At this time, the input level state of the two input terminals of the gate circuit 3 also changes, but as can be seen from the timing chart in FIG. 3, the output state remains at the "H" level state.

Furthermore, the subsequent vertical synchronizing signal pulse is input to one of the input terminals of gate circuit 3 and the clock input terminal of FF2, but since the switching time of gate circuit 3 is faster than the operating time of FF2, the switching operation is performed first. to output a “L” level pulse (waveform E) with a short pulse width,
Clear FF1 and FF2 to return to the initial state (waveforms C and F). In this way, from the Q output of FF2, it is possible to output an "H" level pulse with a pulse width (time To) equal to the period of one field signal, which is sufficient to erase one entire screen. This eliminates the inconvenience of being able to erase only part of the image information within.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a screen erasing signal by a conventional screen erasing circuit, Fig. 2 is a circuit diagram of a screen erasing circuit according to the present invention, and Fig. 3 is an illustration of the operation of the present invention circuit shown in Fig. 2. It is a pulse waveform timing chart diagram for explanation. 1/2...FF, 3...2 input OR gate circuit.

Claims (1)

[Claims for Utility Model Registration] In order to erase image information transmitted using the vertical retrace period of a television video signal and stored in the storage device of a receiver, an image deletion instruction signal transmitted later is decoded. In the screen erasing circuit which inputs the detection signal pulse of the instruction signal outputted from the central processing unit and outputs the screen erasing signal, a screen erasing circuit uses the detection signal pulse as a clock and outputs a predetermined level state as data input. 1
a second flip-flop circuit that uses the synchronization signal pulse output from the synchronization separation circuit of the receiver as a clock and outputs the output of the first flip-flop circuit as a data input; and the second flip-flop circuit. Input the inverted output of the circuit to the first input terminal, input the next synchronization signal pulse after the synchronization signal pulse that activated the second flip-flop circuit to the second input terminal, and make sure that these two input levels match. and a gate circuit that clears the first flip-flop circuit and the second flip-flop circuit by outputting a pulse whose pulse width is a time corresponding to the period of one field from the output terminal of the second flip-flop circuit. A screen erasing circuit that outputs a screen erasing signal having the same pulse width.