JPS6254255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data sampling apparatus for obtaining the sampling pulses necessary to reproduce each bit from a received digital data signal.

Conventionally, this type of data sampling pulse generator compares the position of the sign change point of the input signal with the phase of the clock pulse output from the synchronization oscillator, and based on this phase difference, the clock pulse changes to the input signal. This is achieved by constantly operating a bit synchronizer that corrects the phase of the clock pulse by controlling the frequency of the oscillator so that it is positioned approximately at the center of each bit during the reception period. However, for example, if a microcomputer is used as part of the device to control the clock frequency, the conventional configuration in which the bit synchronizer is constantly operated during the reception period would require other functions other than bit synchronization, such as data acquisition and processing. There is a disadvantage in using the microcomputer in terms of efficiency when executing the processes in the same microcomputer using time-division multiplexing. Furthermore, in a selective calling communication system that selectively calls moving subscriber receivers using a time division multiplexing method, such as in the case of a "pager," the information necessary for each receiver is determined in advance. Since the bit synchronizer is operated during the period before that, synchronization is established by the period that contains the necessary information, and after that, the phase at the time of establishment is maintained. Even if the oscillator frequency is fixed to be equal to the bit frequency of the input signal, accurate data sampling is possible because it can be assumed that synchronization is correctly achieved for a certain period determined by the accuracy of the oscillator.

The present invention provides a data sampling pulse generator suitable for the above-mentioned applications and further suitable for time division multiplex processing in a microcomputer.

An embodiment of the present invention will be described below.

The figure shows an embodiment to which the present invention is applied.

In the figure, 1 is a bit synchronizer, and 2 is a variable frequency divider, which divides the output of the oscillator 3, which generates periodic pulses with a frequency n times the bit frequency of the input signal A (n is an integer), and performs sampling. A clock pulse B is obtained as a pulse. The frequency division ratio is control terminal 2-1,
One of n, n-1, and n+1 is selected by control signals C and D supplied from the control device 4 via 2-2. Reference numeral 5 denotes a shift register of n+1 or more stages driven by a periodic pulse supplied from the oscillator 3, and stores the input signal A sampled by the periodic pulse for at least one bit period. At the time when the clock pulse B is received, the control device 4 receives the data stored in the shift register 5, recognizes the position of the change point, determines whether the timing of the clock pulse B is delayed or advanced, and uses the result. Based on this, control signals C and D that determine the frequency division ratio of the variable frequency divider 2 are supplied to control terminals 2-1 and 2-2. The variable frequency divider 2 uses the frequency division ratio specified by the control signals C and D.
divides the output of the oscillator 3, the same operation is repeated again, and the phase of the clock pulse B is corrected. The data of control signals C and D are latched until new data is obtained next time. Here, the control device 4 is a microcomputer having an input/output interface function, and executes the above operations according to a program stored in a memory in advance.

Reference numeral 6 denotes a timer device for controlling the operation of the above-mentioned bit synchronizer, and alternately and repeatedly supplies a status signal E to the control device 4 for controlling the "activation" and "stopping" of the bit synchronizer. The control device 4 receives the status signal E, and if it is in the "operating" state, continues the operation of the bit synchronizer described above. If it is in the "stop" state, control signals C and D are latched so that the frequency division ratio of frequency divider 2 becomes n from the time when the first clock pulse B is received after entering the "stop" state. , the phase of clock pulse B is not corrected until it is in the "active" state.

By causing the bit synchronizer to operate intermittently as described above, if E is in the "stop" state, the microcomputer composing the control device 4 is made to perform other processing other than bit synchronization. This makes things easier, and it is expected that the efficiency of microcomputer usage will improve.

As described above, according to the present invention, it is possible to improve the usage efficiency of a microcomputer and obtain a data sampling pulse generator with high operating efficiency.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of a data sampling device according to the present invention. DESCRIPTION OF SYMBOLS 1... Bit synchronizer, 2... Variable frequency divider, 3... Periodic pulse generator, 4... Control device, 5... Shift register, 6... Timer device.

Claims (1)

[Claims] 1. A periodic pulse oscillator, a variable frequency divider circuit that divides the output of the pulse oscillator to obtain a clock pulse, and compares the position of the change point of the sign of the input signal with the phase of the clock pulse, and generates a signal according to the phase difference. and a signal that receives the signal obtained by the phase comparison circuit and controls the frequency division ratio of the variable frequency divider circuit so that the clock pulse is located approximately at the center of each bit of the input signal. A bit synchronizer configured with a control circuit, and a timer device that operates the bit synchronizer intermittently. A data sampling pulse generator characterized in that the clock pulse is obtained as a sampling pulse of an input signal by fixing the frequency division ratio of the frequency dividing circuit so that a clock pulse whose previous phase is maintained is obtained.