JPS6311732Y2 - - Google Patents

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Publication number
JPS6311732Y2
JPS6311732Y2 JP1978159814U JP15981478U JPS6311732Y2 JP S6311732 Y2 JPS6311732 Y2 JP S6311732Y2 JP 1978159814 U JP1978159814 U JP 1978159814U JP 15981478 U JP15981478 U JP 15981478U JP S6311732 Y2 JPS6311732 Y2 JP S6311732Y2
Authority
JP
Japan
Prior art keywords
storage container
groove
leads
semiconductor device
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1978159814U
Other languages
Japanese (ja)
Other versions
JPS5575152U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1978159814U priority Critical patent/JPS6311732Y2/ja
Publication of JPS5575152U publication Critical patent/JPS5575152U/ja
Application granted granted Critical
Publication of JPS6311732Y2 publication Critical patent/JPS6311732Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は半導体装置の収納容器に関するもの
で、主としてMOS形半導体装置を対象とした導
電性樹脂製収納容器の改良である。
[Detailed Description of the Invention] The present invention relates to a storage container for semiconductor devices, and is an improvement of a conductive resin storage container mainly intended for MOS type semiconductor devices.

MOS形半導体装置は半導体基板と電極金属間
に静電気がチヤージされやすく、これがかなり高
い電圧になるために半導体装置の機能を一瞬にし
て破壊する場合が少なくない。
In MOS semiconductor devices, static electricity is easily charged between the semiconductor substrate and metal electrodes, and this builds up to a fairly high voltage, which often instantly destroys the functionality of the semiconductor device.

従来このような破壊を防ぐためにMOS構造半
導体装置のリードを導電性スポンジに突き挿して
各リード間を導通せしめるという方法が採られて
いた。
Conventionally, in order to prevent such destruction, a method has been adopted in which the leads of a MOS structure semiconductor device are inserted into a conductive sponge to establish electrical continuity between the leads.

しかし上記導電性スポンジは合成スポンジゴム
などにカーボンCまたは鉄Fe等のごとき導電性
物質の微粉末をスポンジの多孔構造の内部にまで
滲透はたは沈着せしめたものであるため、これに
リードを抜き挿しすると上記導電性物質の微粉末
が飛散して、しばしば試験器やソケツトの中に入
り込み、故障或いは誤動作を引き起こすことがあ
る。
However, the above-mentioned conductive sponge is made of synthetic sponge rubber or the like with fine powder of a conductive substance such as carbon C or iron Fe permeated or deposited into the porous structure of the sponge. When plugged and unplugged, the fine powder of the conductive material is scattered and often gets into the tester or socket, causing failure or malfunction.

そこでこの対策として導電性樹脂を成型加工し
て半導体装置を収納する容器を作製する方法が試
みられているが、従来は半導体装置の大きさ、形
状に合わせて容器を作製していたので、種類が多
く費用がかさむという問題があつた。
As a countermeasure to this problem, attempts have been made to mold conductive resin to create containers for housing semiconductor devices. The problem was that there were a lot of problems and the costs were high.

本考案はこれらの問題点を解消するためになさ
れたもので、導電性微粉末の飛散がなく、且つ汎
用性のある導電樹脂製半導体装置収納容器を提供
することを目的とする。
The present invention has been made to solve these problems, and an object of the present invention is to provide a versatile conductive resin semiconductor device storage container that does not cause scattering of conductive fine powder.

本考案の特徴は、複数のリード端子を有する半
導体装置に収納容器において、幅が表面両側から
底部に向つて次第に狭く形成され、底部が前記リ
ード端子を締めつけ得る程度の幅を有した溝が、
前記リード端子間の最短距離のピツチで平行に配
設されるように導電性樹脂を成形加工してなるこ
とにある。
A feature of the present invention is that, in a storage container for a semiconductor device having a plurality of lead terminals, a groove is formed with a width gradually narrowing from both sides of the surface toward the bottom, and the bottom has a width large enough to tighten the lead terminals.
The conductive resin is molded so that the lead terminals are arranged in parallel at the shortest pitch.

以下本考案の詳細を図面により説明する。 The details of the present invention will be explained below with reference to the drawings.

第1図は本考案の一実施例の要部斜視図であ
る。半導体装置収納容器1は導電性樹脂で作製さ
れており、全面に溝2がピツチpで平行に設けら
れている。本実施例ではピツチpは2.54mmにし
た。また前記溝2は底部3の巾より頂部4の巾の
方が広くなつている。
FIG. 1 is a perspective view of essential parts of an embodiment of the present invention. The semiconductor device storage container 1 is made of conductive resin, and grooves 2 are provided in parallel on the entire surface with a pitch p. In this example, the pitch p was set to 2.54 mm. Further, the width of the top portion 4 of the groove 2 is wider than the width of the bottom portion 3.

上記のごとく本実施例において溝2を2.54mmピ
ツチで平行に配設したのは次の理由による。
The reason why the grooves 2 are arranged in parallel at a pitch of 2.54 mm in this embodiment as described above is as follows.

集積回路、トランジスタアレイなどのように端
子数が多く、しかも端子リードをプリント基板の
孔に挿入固着して使用される半導体装置は、その
端子リードの配置をプリント基板の孔の配置に合
せて作られている。通常のプリント基板は縦横と
も2.54mmピツチで孔が設けられている。換言すれ
ば第2図に示すように2組の平行線群Ai(i=
1,2,…,n)とBj(j=1,2,…,m)を
直交させた時、その両者の交点AiBjがプリント
基板の孔の位置となる。上記半導体装置のリード
の位置は上記プリント基板の孔の位置即ち第2図
の交点AiBjのどれかの位置に対応している。
Semiconductor devices, such as integrated circuits and transistor arrays, which have a large number of terminals and whose terminal leads are inserted and fixed into holes on a printed circuit board, must be manufactured so that the arrangement of the terminal leads matches the arrangement of the holes on the printed circuit board. It is being A typical printed circuit board has holes at a pitch of 2.54 mm both vertically and horizontally. In other words, as shown in FIG. 2, two sets of parallel lines Ai (i=
1, 2, . . . , n) and Bj (j=1, 2, . . . , m) are orthogonally crossed, the intersection point AiBj of the two becomes the position of the hole in the printed circuit board. The position of the lead of the semiconductor device corresponds to the position of the hole of the printed circuit board, that is, any position of the intersection AiBj in FIG. 2.

従つて導電樹脂の板の全面に第2図の交点
AiBjに相当する位置に孔をあけて置けば、前記
半導体装置のリードをその孔に挿入することによ
り収納することができる。しかしこの場合は半導
体装置のリードと上記孔とを位置合せすることが
必要で煩雑である。そこで第2図の2組の平行線
群のうちの一方、例えばBjの平行線群に相当す
る部分を溝にすれば半導体装置を収納するに際し
て位置合わせの煩雑さが除かれて便利である。
Therefore, the intersection point shown in Figure 2 is formed on the entire surface of the conductive resin plate.
By making a hole at a position corresponding to AiBj, the leads of the semiconductor device can be housed by inserting them into the hole. However, in this case, it is necessary to align the leads of the semiconductor device with the holes, which is complicated. Therefore, if one of the two groups of parallel lines in FIG. 2, for example, the portion corresponding to the group of parallel lines Bj, is made into a groove, it is convenient to avoid the complexity of positioning when storing the semiconductor device.

第3図は上述の趣旨で作製された第1図の実施
例に集積回路を収納した状態の一例を示すもので
ある。収納容器1は導電性樹脂を成形加工して製
作され、溝2を2.54mmピツチで平行に設けてあ
る。溝2にはデユアル・イン・ライン型集積回路
(Dual−in−linetype,以下DIT ICと略す)5の
リード6,7が挿入されている。溝2の深さは
DIT IC5の基体の底面8から下の部分のリード
の長さより浅くしてあるので、リード6,7の先
端は溝2の底部3に締めつけられ、各リード間を
導通させ、ICの破壊を防いでいる。リードの配
置はリード6とリード7の間隔は5.08mmであるか
ら図に示すように2ピツチ離れた2本の溝に丁度
収まる。またDIT ICを収納するに際しては、溝
2の頂部4の巾が広くなつているのでリードを挿
入し易い。
FIG. 3 shows an example of the state in which an integrated circuit is housed in the embodiment of FIG. 1, which was manufactured for the purpose described above. The storage container 1 is manufactured by molding conductive resin, and has grooves 2 arranged in parallel at a pitch of 2.54 mm. Leads 6 and 7 of a dual-in-line type integrated circuit (hereinafter abbreviated as DIT IC) 5 are inserted into the groove 2. The depth of groove 2 is
Since the lead length is made shallower than the length of the leads below the bottom surface 8 of the base of the DIT IC 5, the tips of the leads 6 and 7 are tightened to the bottom 3 of the groove 2, creating electrical continuity between the leads and preventing the IC from being destroyed. I'm here. As for the arrangement of the leads, since the distance between leads 6 and 7 is 5.08 mm, they fit exactly into two grooves 2 pitches apart as shown in the figure. Furthermore, when storing the DIT IC, the width of the top 4 of the groove 2 is wide, making it easy to insert the lead.

第4図は他の型の集積回路の底面であつて、リ
ード6は四辺に2列に配置されている。この場合
も相互に隣接するリード間隔及び内側のリードと
外側のリードの間隔ともに2.54mmである。従つて
この場合も第1図実施例の収納容器に収納できる
ことは明らかである。
4 shows the bottom of another type of integrated circuit, in which the leads 6 are arranged in two rows on the four sides. In this case, the spacing between adjacent leads and the spacing between the inner and outer leads are both 2.54 mm. It is therefore clear that this case can also be housed in the housing of the embodiment shown in FIG. 1.

第6図は、第1図の実施例の収納容器に種々の
半導体装置10,20を収納した場合の斜視図で
ある。半導体装置10はDITタイプで、20は4
つの側面に複数のリード端子がそれぞれ設けられ
たタイプである。本実施例の収納容器1は溝2が
リード端子の最短距離である2.54mm(100mil)の
ピツチpで設けられているので、どのような種類
の半導体装置も収容できる。IC10はリード端
子がピツチp間隔で設けられ、IC20は隣接す
るリード端子間はピツチpで対向する辺のリード
端子間はピツチ5pで設けられている。もちろん
第4図の如くリードが配列されたICも収容でき
る。
FIG. 6 is a perspective view of the storage container of the embodiment shown in FIG. 1 in which various semiconductor devices 10 and 20 are stored. The semiconductor device 10 is a DIT type, and the semiconductor device 20 is a 4
This type has multiple lead terminals on each side. In the storage container 1 of this embodiment, the grooves 2 are provided at a pitch p of 2.54 mm (100 mil), which is the shortest distance between lead terminals, so that any type of semiconductor device can be accommodated. The IC 10 has lead terminals arranged at a pitch p, and the IC 20 has lead terminals arranged at a pitch p between adjacent lead terminals, and a pitch 5 p between lead terminals on opposing sides. Of course, an IC with leads arranged as shown in Fig. 4 can also be accommodated.

第5図は、第1図、第3図、及び第6図に示し
た半導体収納容器の溝方向と垂直な方向の断面図
である。本実施例はミゾ2の底部3の巾をリード
の太さより狭くしてある。リードをこの溝2に挿
入して上部より押圧すれば、リードの先端は底部
3に食い込み固く保持されるので、各リード間の
導通が完全になると同時に、少々の振動では抜け
落ちることもなく、取扱上便利になる。
FIG. 5 is a cross-sectional view of the semiconductor storage container shown in FIGS. 1, 3, and 6 in a direction perpendicular to the groove direction. In this embodiment, the width of the bottom 3 of the groove 2 is made narrower than the thickness of the lead. When a lead is inserted into this groove 2 and pressed from the top, the tip of the lead bites into the bottom 3 and is firmly held, ensuring complete continuity between each lead and preventing it from falling out even with slight vibration, making it easy to handle. It becomes more convenient.

更に集積回路の小型化、或いは集積度の向上な
どにより、リード間隔が狭くなつた場合には、そ
のリード間隔に溝のピツチを合せて本考案の趣旨
の収納容器を作ることができる。
Furthermore, if the lead spacing becomes narrower due to the miniaturization of integrated circuits or the increase in the degree of integration, the storage container according to the present invention can be made by matching the pitch of the grooves to the lead spacing.

以上説明したごとく本考案の収納容器によれ
ば、MOS型半導体装置の保護のための静電気対
策機能を損うことなく、導電性微粉末が埃として
飛散しないので機器の故障や誤動作を防ぐことが
でき、しかも汎用性を持たせることができた。
As explained above, according to the storage container of the present invention, the electrostatic countermeasure function for protecting MOS type semiconductor devices is not impaired, and conductive fine powder does not scatter as dust, thereby preventing device failures and malfunctions. We were able to make it possible and have versatility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す要部斜視図、
第2図は本考案の溝の位置と半導体装置のリード
の位置との関係を説明するための図面、第3図は
第1図の一実施例をDIT ICに使用した時の状態
を示す要部斜視図、第4図はDIT ICとは異なる
型の集積回路のリードの配置図、第5図は、本考
案の半導体収納容器の溝方向と垂直な方向の断面
図、第6図は種々の半導体装置を収納した場合の
斜視図である。 1……導電性樹脂製半導体装置収納容器、2…
…溝、3……溝の底部、4……溝の頂部、p……
溝のピツチ。
FIG. 1 is a perspective view of essential parts showing an embodiment of the present invention;
Fig. 2 is a drawing for explaining the relationship between the position of the groove of the present invention and the position of the lead of the semiconductor device, and Fig. 3 is a diagram showing the state when the embodiment of Fig. 1 is used in a DIT IC. FIG. 4 is a lead arrangement diagram of an integrated circuit of a different type from DIT IC, FIG. 5 is a cross-sectional view of the semiconductor storage container of the present invention in a direction perpendicular to the groove direction, and FIG. 6 is a diagram showing various types of integrated circuits. FIG. 1... conductive resin semiconductor device storage container, 2...
...Groove, 3...Bottom of the groove, 4...Top of the groove, p...
The pitch of the groove.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のリード端子を有する半導体装置の収納容
器において、幅が表面両側から底部に向つて次第
に狭く形成され、底部が前記リード端子を締めつ
け得る程度の幅を有した溝が、前記リード端子間
の最短距離のピツチで平行に配設されるよう導電
性樹脂を成形加工してなることを特徴とする半導
体装置の収納容器。
In a storage container for a semiconductor device having a plurality of lead terminals, a groove whose width is gradually narrowed from both sides of the surface toward the bottom, and whose bottom part has a width enough to tighten the lead terminals is the shortest distance between the lead terminals. A storage container for semiconductor devices characterized by being formed by molding a conductive resin so that they are arranged in parallel at a pitch.
JP1978159814U 1978-11-20 1978-11-20 Expired JPS6311732Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1978159814U JPS6311732Y2 (en) 1978-11-20 1978-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1978159814U JPS6311732Y2 (en) 1978-11-20 1978-11-20

Publications (2)

Publication Number Publication Date
JPS5575152U JPS5575152U (en) 1980-05-23
JPS6311732Y2 true JPS6311732Y2 (en) 1988-04-05

Family

ID=29152971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1978159814U Expired JPS6311732Y2 (en) 1978-11-20 1978-11-20

Country Status (1)

Country Link
JP (1) JPS6311732Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925821U (en) * 1972-06-06 1974-03-05

Also Published As

Publication number Publication date
JPS5575152U (en) 1980-05-23

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