JPS63164341A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS63164341A JPS63164341A JP30964186A JP30964186A JPS63164341A JP S63164341 A JPS63164341 A JP S63164341A JP 30964186 A JP30964186 A JP 30964186A JP 30964186 A JP30964186 A JP 30964186A JP S63164341 A JPS63164341 A JP S63164341A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silica
- insulating film
- conductive layer
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 239000007791 liquid phase Substances 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 82
- 239000000377 silicon dioxide Substances 0.000 abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 26
- 239000010410 layer Substances 0.000 abstract description 23
- 239000011229 interlayer Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- 150000003377 silicon compounds Chemical class 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 239000007888 film coating Substances 0.000 abstract 1
- 238000009501 film coating Methods 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 210000004907 gland Anatomy 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XAYKIPCPOCXUBY-UHFFFAOYSA-N 2-[3-(2-hydroxypropyl)pyridin-1-ium-1-yl]acetate Chemical compound CC(O)CC1=CC=C[N+](CC([O-])=O)=C1 XAYKIPCPOCXUBY-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に係り、特に層
間絶縁膜の平担化方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a method for leveling an interlayer insulating film.
従来、層間絶鍬膜を平らにする技術には、常圧ＣＶＤに
よる高磯度ＰＥＧ（リンシリケートガラス）喚を成長さ
せた後に、熱処理にてフローさせる方法、あるいは低濃
度ＰＳＧ膜成膜成長後膜縁膜部を液相絶縁膜をスピンコ
ート（以下シリカ塗布と称す）にてなだらかにする方法
が多く用いられている。Conventionally, techniques for flattening the interlayer insulation film include growing a high-strength PEG (phosphosilicate glass) film by atmospheric pressure CVD and then flowing it through heat treatment, or forming a low-concentration PSG film and then growing it. A method is often used in which the edge of the film is smoothed by spin coating (hereinafter referred to as silica coating) with a liquid phase insulating film.
前述した従来の高礎度Ｐ８Ｇ膜の熱処８！フロー法は、
フローさせる熱処理温度が烏いため、拡散層が深くなり
、素子の微細化の妨げとなる。また、高濃度ＰＥＧ模と
金属配線とを直接接触させると、金り配線（特にアルミ
ニウム）の腐食が起こるため、間に低濃度Ｐ Ｓ Ｇｍ
’ｅｆｉさむ必要があり、必然的にコンタクト形成ｒｉ
２度抜きとなシ、製造工Ｓ！は長く、替細化にも適して
いるとｒｔ言えな―。Heat treatment of the conventional high-grade P8G film mentioned above 8! The flow method is
Since the flow heat treatment temperature is high, the diffusion layer becomes deep, which hinders the miniaturization of devices. In addition, if the high concentration PEG pattern and metal wiring are brought into direct contact, the metal wiring (especially aluminum) will corrode, so if the low concentration PEG pattern is brought into direct contact with the metal wiring, the low concentration P S Gm
'efi needs to be removed, which inevitably leads to contact formation
Twice without exception, manufacturing engineer S! It can be said that it is long and suitable for thinning.
一方、シリカ塗布法は、比較的低温で低温濃度ＰＥＧ膜
の平担化を実現できるため、索子の微細化が可能となシ
、またコンタクト形成は一度抜きで製造工程が雉かくな
る。しかしながら、シリカ塗布法にもいくつかの欠点が
ある。これを、第３図（Ａ）乃至（０を参照して、よシ
詳しく述べる。On the other hand, the silica coating method can realize flattening of a low-concentration PEG film at a relatively low temperature, so it is possible to miniaturize the cables, and the manufacturing process is complicated because contact formation is omitted once. However, the silica coating method also has some drawbacks. This will be described in more detail with reference to FIGS. 3(A) to (0).
まず、第３図（５）において、半導体基板１上のフィー
ルド絶縁＠２の上に、多結晶シリコン配線３を部分的に
形成する。First, in FIG. 3(5), polycrystalline silicon wiring 3 is partially formed on field insulation @2 on semiconductor substrate 1. Next, as shown in FIG.
第３図向において、前記多結晶シリコン配線３を薄いシ
リコン酸化ｇＡ４で穫った後、低濃度ＰＳＧ膜６を比較
的厚く成長させ、
第３図０に示すように、第１シリカ５の塗布を行なう０
通常、シリカ塗布は、段部を充分埋め込むため、第２シ
リカ５′を塗布する必要がおる。In the direction of FIG. 3, after the polycrystalline silicon wiring 3 is coated with a thin silicon oxide layer 4, a low concentration PSG film 6 is grown relatively thickly, and a first silica layer 5 is applied as shown in FIG. 0
Normally, when applying silica, it is necessary to apply a second silica 5' in order to sufficiently embed the stepped portion.
次に、
第３鋤に示すように、平担化された層間絶縁膜上を横切
る金篇配１１ｅ１８の様子を表わしている。Next, as shown in the third plow, the state of the gold plate 11e18 crossing the flattened interlayer insulating film is shown.
ところで、多結晶シリコン配組３間の間隔が狭くなった
楊合−低濃度ＰＥＧ膜６の段部におけるアスペクト比は
大きくなシ、シリカ塗布によるシリカ埋め込みは困難と
なる。第３図（均に示すように、低濃度ＰＳＧ＠６とシ
リカ５との間に空洞１１ができたり、第１シリカ５と第
２シリカ５′との間に隙間のある空洞１２が生じたシす
る。特に、第１シリカ５と第２シリカ５′の間の空洞１
２がはなはだしきときは、第３図（Ｆ″Ｉに示すように
、第２シリカ５′がはがれ、結果的にこのはがれ部１３
によジ、金属配線８が段切れを生じ、牛導体集積回路装
置二の製造歩留り上、および信頼性上重大な問題となる
。By the way, the aspect ratio of the stepped portion of the low-concentration PEG film 6 where the distance between the polycrystalline silicon arrays 3 is narrowed is large, making it difficult to embed silica by applying silica. Figure 3 (As shown in Figure 3, a cavity 11 was created between the low concentration PSG@6 and the silica 5, and a cavity 12 with a gap was created between the first silica 5 and the second silica 5'. In particular, the cavity 1 between the first silica 5 and the second silica 5'
When the second silica 5' is exposed too much, the second silica 5' peels off, as shown in FIG.
This causes the metal wiring 8 to break, which poses a serious problem in terms of manufacturing yield and reliability of the conductor integrated circuit device 2.
前述した従来のシリカ塗布法における多結晶シリコン配
線間隔とシリカ不良との関係を第４図に示す。同図にお
いて、低濃度Ｐ８Ｇ膜厚１．０μｍ一定で、たとえば多
結晶シリコン膜厚が６００ＯＡの場合、多結晶シリコン
配線間隔が１．８μｍ以下になると、シリカの空洞やは
がれが生じる。FIG. 4 shows the relationship between the polycrystalline silicon wiring spacing and silica defects in the conventional silica coating method described above. In the figure, when the low concentration P8G film thickness is constant at 1.0 μm and the polycrystalline silicon film thickness is 600 OA, for example, when the polycrystalline silicon wiring interval becomes 1.8 μm or less, silica cavities and peeling occur.
本発明の目的は、前記間廟点を解決し、不良を低減させ
、微細化に適し先生導体集積回路装置の製造方法を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a conductor integrated circuit device that solves the above-mentioned problems, reduces defects, and is suitable for miniaturization.
本発明の構成は、半導体基板の一主面上に厚いフィール
ド絶縁膜を形成する工程と、前記フィールド絶縁膜上に
複数の導電層配線を形成する工程と、導電層配線を薄い
絶縁膜で徨った後、シリカ塗布にて前記導電層配線の間
をシリカで埋め込み、熱処理にて絶縁膜に変化させ平担
化する工程と、次に低濃度ＰＳＧ膜を厚く成長させ、フ
ォトレジストを表面が平担化するまで厚く塗布し、前記
フォトレジストを表向が平担化するまで厚く塗布し、前
記フォトレジストと低濃度ＰＥＧ膜をドライエブチにて
、前記導電層配線を扱う薄い絶縁膜に違°しない程度に
エッチバックする工程と、続いて栴び低濃度Ｐ２Ｏ膜を
所望の厚さに成長させる工程と、最後に第２の複数の導
電層配線を形成する工程とを備えていることを特徴とす
る。The structure of the present invention includes a step of forming a thick field insulating film on one main surface of a semiconductor substrate, a step of forming a plurality of conductive layer wirings on the field insulating film, and a step of forming the conductive layer wirings with a thin insulating film. After that, silica is applied to fill in the spaces between the conductive layer wirings, and heat treatment is performed to transform it into an insulating film and flatten it. Next, a low concentration PSG film is grown thickly, and the photoresist is made flat on the surface. The photoresist is applied thickly until the surface becomes flat, and the photoresist and the low concentration PEG film are coated in a dry etching process to form a thin insulating film that handles the conductive layer wiring. It is characterized by comprising the steps of etching back to a level that does not affect the conductive layer, followed by growing a thinned low-concentration P2O film to a desired thickness, and finally forming a second plurality of conductive layer wirings. shall be.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図ＩＡ）乃至０は本発明の一実施例を工１！＋−に
説明する断面図である。まず、第１図（５）において、
シリコン半導体基板ｌ上に熱酸化により、厚いフィール
ドｅシリコン酸化腺２を形成し、このフィールド酸化膜
２の上にＬＰＣＶＤ法によ！ａ６０００λ程度の多結晶
シリコン層を形成し、ホトリングラフィ技術により多結
晶シリコン配線層のノ（ターニングを行ない、多結晶シ
リコン膜３を形成する。FIG. 1 IA) to 0 represent an embodiment of the present invention. It is a sectional view explaining +-. First, in Figure 1 (5),
A thick field silicon oxide gland 2 is formed on a silicon semiconductor substrate l by thermal oxidation, and then a thick field silicon oxide gland 2 is formed on this field oxide film 2 by the LPCVD method! A polycrystalline silicon layer having a thickness of approximately 6000λ is formed, and the polycrystalline silicon wiring layer is turned by photolithography technology to form a polycrystalline silicon film 3.
次に第１図（Ｂ）において、前記多結晶シリコン配線膜
３を、熱酸化によシ、薄い多結晶シリコン酸化膜４で機
った後、シリカ・フィルム等の有機シリコン化合物をス
ピンナで塗布し、熱処理によシリコン酸化製に変化させ
て第１のシリカ５を形成し１、さらに前記同様の方法に
より、第２シリカ５′を形成し、多結晶シリコン配ｍ膜
の方法により、第２シリカ５′を形成し、多結晶シリコ
ン配線膜３上の平担化を行なう。Next, in FIG. 1(B), the polycrystalline silicon wiring film 3 is formed into a thin polycrystalline silicon oxide film 4 by thermal oxidation, and then an organic silicon compound such as silica film is coated with a spinner. Then, a first silica 5 is formed by heat treatment to make it silicon oxide, a second silica 5' is formed by the same method as described above, and a second silica 5 is formed by a polycrystalline silicon patterning method. Silica 5' is formed and leveled on the polycrystalline silicon wiring film 3.
第１図Ｃにおいて、低濃度ＰＥＧ膜６を常圧ＣＶＤ法に
より１．５μｍ程度の厚さに成長させ、さらにこの低濃
度Ｐ８Ｇ［６の表面の平担化を図るために、密着性が悪
く、非常にダレやすり、ホトレジスト７を２．０μｍ程
度塗布し、レジスト７と低濃度ＰＳＧ膜６の選択比の等
しい条件で、例えばＣＨＰＢ、Ｃ２Ｆ＠ 、Ｈｅ１ＣＯ
１を添付したガスでエッチバックする。この際、ドライ
エッチは、多結晶シリコン配線膜３を櫟う薄い多結晶シ
リコン酸化膜４に達しない極度実施する。In FIG. 1C, a low-concentration PEG film 6 is grown to a thickness of about 1.5 μm by normal pressure CVD, and in order to flatten the surface of this low-concentration P8G [6], the adhesion is poor. , apply a photoresist 7 to a thickness of about 2.0 μm using a very sagging sandpaper, and under conditions where the selectivity of the resist 7 and the low-concentration PSG film 6 are equal, for example, CHPB, C2F@, He1CO
Etch back with the gas attached to 1. At this time, the dry etching is carried out to the extent that it does not reach the thin polycrystalline silicon oxide film 4 that spans the polycrystalline silicon wiring film 3.
さらに、第１図口において、再び低濃度ＰＳＧ膜６′を
１．０μｍ程度の厚さに成長させて、層間絶縁膜の平担
化を完了させる。Furthermore, as shown in FIG. 1, a low concentration PSG film 6' is again grown to a thickness of about 1.0 μm to complete the leveling of the interlayer insulating film.
以上述べた層間絶縁膜の平担化技術を用いる事で、層間
絶縁膜上に形成された金属配線８は、従来の多結晶シリ
コン配線間の間隔を狭くした際見られた、金属配線の段
切れ等の不良はなくなシ、極めてフラットな配硼が形成
される。By using the interlayer insulating film flattening technique described above, the metal wiring 8 formed on the interlayer insulating film can be made into a layered metal wiring that is similar to that seen when the spacing between conventional polycrystalline silicon wirings is narrowed. There are no defects such as cuts, and an extremely flat slag is formed.
本実施例における多結晶シリコン配線間隔とシリカ不良
との関係を第５図に示す、低濃度ＰＳＧ膜厚１．０μｍ
、多結晶シリコン膜厚６０００λの条件にて、多結晶シ
リコン配線間隔が０．６μｍまで可能であり、この寸法
は現在版先端のリングラフィ技術でパターニングできる
極度の数値である。The relationship between the polycrystalline silicon wiring spacing and silica defects in this example is shown in Figure 5, with a low concentration PSG film thickness of 1.0 μm.
Under the condition that the polycrystalline silicon film thickness is 6000λ, the polycrystalline silicon wiring spacing can be up to 0.6 μm, and this dimension is an extreme value that can be patterned with the current state-of-the-art phosphorography technology.
第２図（５）乃至ＩＱｒｉ本発明の他の実施例の断面図
である。第２図ｒ（ＡＪにおいて、第１の実ｍｆｌＩで
述べたｉ！ｋＦ工程の縦断面図の第１図口を示している
。FIG. 2(5) to IQri are sectional views of other embodiments of the present invention. Figure 2r (AJ shows the opening in Figure 1 of the longitudinal sectional view of the i!kF process described in the first example mflI).
ただし、多結晶シリコン配線膜３ｒｉ省略され、狽数の
金属配線８が低濃度）’８０［６上に形成されている。However, the polycrystalline silicon wiring film 3ri is omitted, and a small number of metal wirings 8 are formed on the low concentration )'80[6.
金属配線８ｒｉ、例えはスパッタ法にてアルミニウムを
６００ ＯＡｉ度成長させ、ホトリングラフィ技術によ
シアルミニウム配線のパターニングを行なう。For the metal wiring 8ri, for example, aluminum is grown to a thickness of 600 OAi by sputtering, and the aluminum wiring is patterned by photolithography.
次に第２１Ｖ（Ｂ）において、シリコンをターゲ雫トと
し、Ｎ２による反応性スパッタ法により、シリコン窒化
膜９を１５００Ａ程度成長させ、金属配線８を薄い絶縁
膜で覆う。Next, in the 21st V (B), using silicon as a target, a silicon nitride film 9 of about 1500 Å is grown by reactive sputtering using N2, and the metal wiring 8 is covered with a thin insulating film.
第２図（ｑにおいて、シリカ塗布法により、金属配＃８
間をシリカ５で埋め込んだ後、たとえば〆３５０℃程度
で５ｉＨ４−ＮＨ３−Ｎ３系のプラズマＣＶＤにより、
シリコン窒化膜１０を１，５μｍ程度の厚さに成長させ
、次にホトレジストアを２．０μｍ４度塗布し、レジス
ト７とプラズマ・シリコン窒化膜１０の選択比の尋しい
条件でエッチバックする。この際ドライエ、チは、金属
配＊８を轡うスパッタシリコン窒化膜９に達しない程度
に実施する。Figure 2 (in q, metal wiring #8 is coated using the silica coating method.
After filling the gap with silica 5, for example, by 5iH4-NH3-N3 based plasma CVD at about 350℃,
The silicon nitride film 10 is grown to a thickness of about 1.5 μm, and then photoresist is applied four times to a thickness of 2.0 μm, and etched back under conditions that provide a selective ratio between the resist 7 and the plasma silicon nitride film 10. At this time, dry etching is performed to such an extent that it does not reach the sputtered silicon nitride film 9 covering the metal wiring *8.
さらに、第２（！￥ｊＯにおいて、再びプラズマシリコ
ン窒化膜１０′上に例えば膜専１．０μｍ程度のアルミ
ニウムの金属配＃Ｍ８′を形成する。Furthermore, in the second step (!\jO), a metal wiring #M8' made of aluminum and having a thickness of approximately 1.0 μm is again formed on the plasma silicon nitride film 10'.
以上の第２の実施例に述べたように、層間絶縁膜はシリ
コン窒化膜でも可能であシ、機織化の進んだアルミニウ
ムの二層配線構造が比較的容易に形成できる利点がある
。As described in the second embodiment above, the interlayer insulating film can also be a silicon nitride film, which has the advantage that a highly woven two-layer aluminum wiring structure can be formed relatively easily.
以上説明したように、本発明は、従来の層間絶縁膜の平
担化技術の欠点をなくし、以下に述べる効果がある。As explained above, the present invention eliminates the drawbacks of the conventional technique for leveling an interlayer insulating film, and has the following effects.
（１） ４ｉｌｔ層配線の集積匿を３倍にできる。つ
まり、導電層の膜厚が６ｔＪＵＯＡの場合、従来の層間
絶縁膜の平担化技術では導電層配線間隔ｒｉ１．８μｍ
が限界だが、本発明によれば、０．６μｍ″！！で可能
である。(1) The integration density of 4ilt layer wiring can be tripled. In other words, when the film thickness of the conductive layer is 6tJUOA, the conductive layer wiring spacing ri is 1.8 μm using the conventional interlayer insulating film flattening technology.
is the limit, but according to the present invention, it is possible with 0.6 μm''!!
（り 信頼性のｉ＃ｌ−多層配線が形成で色る。(Reliable i#l-Multilayer interconnection changes in formation.
従来の技術では層間絶縁膜上の導電層配線間隔を狭めて
いくと、層間絶縁膜上の導電層成層が段切れを起こすよ
うな不良を生じたが、本発明ではこの不良は生じない０
本発明においても導電層配線間隔が０．６μｍ以下にな
れば不良を生じるが、０．６μｍという数値以下のパタ
ーニングは、現在の最先端のリングラフィ技術をもって
しても難しいからである。In the conventional technology, when the distance between the conductive layer wiring on the interlayer insulating film was narrowed, defects such as disconnection of the conductive layer on the interlayer insulating film occurred, but in the present invention, this defect does not occur.
Even in the present invention, defects occur if the conductive layer wiring spacing is 0.6 μm or less, but patterning with a value of 0.6 μm or less is difficult even with the current state-of-the-art phosphorography technology.
本発明は、特に大規模ＬＳＩの層間絶縁膜の平担化技術
を提供するものであるが、バイポーラ。The present invention particularly provides a technique for flattening the interlayer insulating film of a large-scale LSI, especially a bipolar one.
ＭＯ８等を含むあらゆる半導体集積回路装置の層間絶縁
膜の平担化技術として適用できる。It can be applied as a flattening technique for interlayer insulating films of all semiconductor integrated circuit devices including MO8 and the like.
第１図四乃至第１図（Ｄｌは本発明の一実施例の半導体
集積回路装置の製造方法をｆＪＩ造工程順に示す断面図
、第２図ＩＡ）乃至第２図（ＤＪｒｔ本発明の他の実施
例の半導体集積回路装置の製造方法を工程ＪＩｊｌに示
す断面図、第３回内乃至第３図ｔａｒｉ従来の層間絶縁
膜の平担化を製造工程順に示す断面図、第３図（１、０
’）はいずれも従来の製造方法の欠点を示す断面図、第
４図は従来のポリシリコン配線間隔とポリシリコン膜厚
との関係を示す特性図、第５図は本発明の実施例のポリ
シリコン配１１１ｉ１１′＆ｉ１隔とポリシリコン膜厚
との関係を示す特性図である。
１・・・・・・半導体基板、２・・・・・・フィールド
酸化層、３・・・・・・多結晶シリコン族、４・・・・
・・多結晶シリコン酸化層、５・・・・・・第１のシリ
カ、５′・・・・・・第２のシリカ、６．６’・・・・
・・低濃度Ｐ２Ｏ膜、７・・・・・・ホトレジスト、８
．８’・・・・・・金属配線、９・・・・・・スパヴタ
シリコン窒化展、１０．１０’・・・・・・プラズマシ
リコン窒化膜、１１・・・・・・シリカ空洞、１２・・
・・・・第１シリカと第２シリカの間の空洞、１３・・
・・・・第２シリカはがれ部。
第３図4 to 1 (Dl is a cross-sectional view showing the manufacturing method of a semiconductor integrated circuit device according to one embodiment of the present invention in the fJI manufacturing process order, and FIG. 2 IA) to FIG. Cross-sectional views showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment in the steps JIjl, 3rd to 3rd cross-sectional views showing the conventional planarization of the interlayer insulating film in the order of the manufacturing steps, FIGS. 0
') are cross-sectional views showing the drawbacks of the conventional manufacturing method, FIG. 4 is a characteristic diagram showing the relationship between the conventional polysilicon interconnect spacing and polysilicon film thickness, and FIG. FIG. 7 is a characteristic diagram showing the relationship between the silicon interconnections 111i11'&i1 distance and the polysilicon film thickness. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Field oxide layer, 3...Polycrystalline silicon group, 4...
...Polycrystalline silicon oxide layer, 5...First silica, 5'...Second silica, 6.6'...
...Low concentration P2O film, 7...Photoresist, 8
．． 8'...Metal wiring, 9...Spavta silicon nitride, 10.10'...Plasma silicon nitride film, 11...Silica cavity, 12...
...Cavity between the first silica and the second silica, 13...
...Second silica peeling part. Figure 3
Claims (1)
記第１の絶縁膜上に複数の第１の導電層配線を形成する
工程と、前記第１の導電層配線を薄い第２の絶縁膜で覆
う工程と、液相絶縁膜をスピンコートにて、前記第１の
導電層配線間に埋め込み、熱処理にて第３の絶縁膜に変
化させ、表面を平担化する工程と、第４の絶縁膜を前記
第１の導電層膜厚より厚く成長させる工程と、ホトレジ
ストを厚く塗布して表面を平担化する工程と、前記ホト
レジストおよび前記第４の絶縁膜をドライエッチにて、
前記第１の導電層配線上の前記第２の絶線膜に達しない
程度にエッチバックする工程と、第５の絶縁膜を所望の
厚さに成長させる工程と、前記第５の絶縁膜上に第２の
導電層配線を形成する工程とを備えていることを特徴と
する半導体集積回路装置の製造方法。forming a first insulating film on the surface of a semiconductor substrate; forming a plurality of first conductive layer wirings on the first insulating film; and forming a plurality of first conductive layer wirings on a thin second insulating film. a step of covering with an insulating film, a step of embedding a liquid phase insulating film between the first conductive layer wirings by spin coating, changing it into a third insulating film by heat treatment, and flattening the surface; A step of growing the fourth insulating film to be thicker than the first conductive layer film thickness, a step of applying a thick photoresist to flatten the surface, and dry etching the photoresist and the fourth insulating film,
a step of etching back to an extent that does not reach the second insulating film on the first conductive layer wiring; a step of growing a fifth insulating film to a desired thickness; 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a second conductive layer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61309641A JP2637726B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61309641A JP2637726B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63164341A true JPS63164341A (en) | 1988-07-07 |
| JP2637726B2 JP2637726B2 (en) | 1997-08-06 |
Family
ID=17995486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61309641A Expired - Lifetime JP2637726B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2637726B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226480A (en) * | 1991-12-04 | 1993-09-03 | Nec Corp | Manufacture of semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245254A (en) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | Formation of interlayer insulation film |
| JPS6151848A (en) * | 1984-08-21 | 1986-03-14 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61107745A (en) * | 1984-10-30 | 1986-05-26 | Nec Corp | Manufacture of semiconductor device |
| JPS61114559A (en) * | 1984-11-09 | 1986-06-02 | Nec Corp | Semiconductor device |
| JPS63142A (en) * | 1986-06-19 | 1988-01-05 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-12-26 JP JP61309641A patent/JP2637726B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60245254A (en) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | Formation of interlayer insulation film |
| JPS6151848A (en) * | 1984-08-21 | 1986-03-14 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61107745A (en) * | 1984-10-30 | 1986-05-26 | Nec Corp | Manufacture of semiconductor device |
| JPS61114559A (en) * | 1984-11-09 | 1986-06-02 | Nec Corp | Semiconductor device |
| JPS63142A (en) * | 1986-06-19 | 1988-01-05 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05226480A (en) * | 1991-12-04 | 1993-09-03 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2637726B2 (en) | 1997-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0360055A (en) | Manufacturing method of integrated circuit | |
| JPS6358944A (en) | Method of forming mutual junction level and via stud | |
| US6297145B1 (en) | Method of forming a wiring layer having an air bridge construction | |
| JPH0418701B2 (en) | ||
| US6376357B1 (en) | Method for manufacturing a semiconductor device with voids in the insulation film between wirings | |
| JPS63164341A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2628339B2 (en) | Method for manufacturing semiconductor device | |
| JPS586306B2 (en) | Handout Taisouchino Seizouhouhou | |
| JPS59205735A (en) | Manufacture of semiconductor device | |
| JPS63258043A (en) | Manufacture of semiconductor device | |
| JP2702010B2 (en) | Method for manufacturing semiconductor device | |
| JP2874216B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS61287245A (en) | Multilayer interconnection method | |
| JPS60115234A (en) | Preparation of semiconductor device | |
| JPH07161720A (en) | Semiconductor device and its manufacture | |
| JPS60175439A (en) | Method for forming multilayer interconnection | |
| JPH0797583B2 (en) | Method for forming interlayer insulating film | |
| JPS6281732A (en) | Insulating film planarization method | |
| JPS6134956A (en) | Method for forming wiring layer | |
| JPH088249A (en) | Method for forming interlayer insulation film | |
| JPH0384927A (en) | Manufacture of semiconductor device provided with multilayer interconnection | |
| JPH0298960A (en) | Manufacture of semiconductor device | |
| JPH0927492A (en) | Manufacture of semiconductor device | |
| JPH05160126A (en) | Formation of multilayer wiring | |
| JPH01231354A (en) | Formation of connection hole of semiconductor device |