JPS6325780Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a circuit for delay processing a signal, and allows the delay time to be arbitrarily set by controlling DC voltage, and is suitable for integrated circuits, such as It can be applied to color television receivers, etc.

Generally, when the composite video signal of a color television receiver is separated into a luminance signal and a chrominance signal by a signal separation circuit, the chrominance signal has a narrow band, so it may lag behind the luminance signal during the signal processing process. Are known. Therefore, if things continue as they are, later on the cathode ray tube,
Various problems occur when these signals are input and imaged. Therefore, the luminance signal is delayed for a predetermined period of time to relatively correct the delay of the color signal, thereby performing phase compensation. A composite video signal processing circuit based on such a configuration will be explained with reference to FIG.

In FIG. 1, a video intermediate frequency signal is supplied to an input terminal 1, and this terminal 1 is connected to a video intermediate frequency detection circuit 2 (referred to as a PIF circuit). This PIF circuit 2 outputs a composite video signal and is connected to a video signal amplification circuit 3. This video signal amplification circuit 3 is branched into a first signal path that processes the luminance signal and a second signal path that processes the color signal, and the branch point 4 adjusts the band of the carrier color signal. and a delay line 6 which also serves as a band filter for the luminance signal.

The band adjustment circuit 5 is a type of filter that extracts and outputs a carrier color signal from a composite video signal, and
Its output terminal is connected to a color demodulation circuit 7.
The color demodulation circuit 7 band-amplifies the carrier color signal, demodulates the color signal using a reference subcarrier provided separately for extracting the color signal, and outputs the color signal to the output terminal 8. On the other hand, the delay line 6 uses lumped constant or distributed constant type individual components,
The video signal is delayed by a predetermined amount of time, and the luminance signal component is extracted as the output. This delay line 6 is connected to an output terminal 10 via a luminance signal amplification circuit 9, and is synthesized with the color signal by a synthesis circuit (not shown). Thus, by delaying the luminance signal by the delay line 6, the delay in the carrier color signal is compensated for.

FIG. 2 is a block diagram showing another conventional example using a comb filter circuit to separate a luminance signal and a carrier color signal. To explain the configuration of Figure 2,
The composite video signal from the video signal amplification circuit 3 is supplied to one input end of an adder 12 and a subtracter 14 via conductors 11 and 13, respectively, and is further supplied to one input terminal of an adder 12 and a subtracter 14 using a charge transfer element which is a delay element. Horizontal period delay circuit (hereinafter referred to as 1H delay circuit) 1
5 to the other input ends of the adder 12 and the subtracter 14, respectively. The circuit with the above configuration is the comb filter 16. The characteristics of this comb filter 16 are determined by the transfer pulse period from the clock generator 17 that supplies control pulses to the 1H delay circuit 15, and the luminance signal is transmitted from the adder 12 and the luminance signal is transmitted from the subtracter 14. Carrier color signals can be output respectively.

The output of the adder 12 of this comb filter 16 is connected to a delay circuit 18 composed of charge transfer elements in the same manner as described above, and this delay circuit 18 is connected to the adder 20 via a first low-pass filter 19. Connected to one input end.

On the other hand, the output of the subtracter 14 of the comb filter 16 is connected to the other input terminal of the adder 20 via the second low-pass filter 21, and is also connected to the output terminal 8' via the band adjustment circuit 5. The carrier color signal is output to the Said second low pass filter 2
1 removes high frequency components from the output of the subtracter 14 to obtain a vertical contour correction signal (hereinafter referred to as VD signal), and supplies the VD signal to the adder 20.

In the configuration shown in FIG. 2, the VD signal is sent to the adder 20.
The reason why the signal is supplied to the luminance signal and added to the luminance signal is to correct the fact that the vertical contour of the luminance signal may be disturbed due to the addition of a signal delayed by one horizontal period and a signal that is not delayed. be. in this case,
Since the VD signal, which is a low frequency component, has a narrow band compared to the luminance signal, a delay occurs when it passes through the low frequency filter 21. Therefore, the luminance signal is delayed by the delay amount by the delay circuit 18 to correct the composite phase with the VD signal. The luminance signal is further delayed by a delay line 6 to compensate for the time delay of the color signal.

In FIG. 2, if the delay time of the VD signal due to passing through the low-pass filter 21 is τ ₁ and the delay time due to the carrier color signal passing through the band adjustment circuit 5 is τ ₂ , then the delay time of the delay circuit 18 is τ If it is set to ₁ , the delay of the VD signal with respect to the luminance signal can be compensated for. Furthermore, if the delay time of the delay line 6 is set to (τ ₂ - _{τ 1} ), the output of the adder 12 is delayed by τ ₁ in the delay circuit 18, and further delayed by τ ₂ - _{τ 1} in the delay line 6, so the total delay time is τ ₁ +(τ ₂ −τ ₁ )=τ ₂ , which corresponds to the delay time caused by the carrier color signal passing through the band adjustment circuit 5, and the phase of the luminance signal and the carrier color signal can be compensated.

In this way, the conventional example shown in FIGS. 1 and 2 is
In both cases, a distributed constant or lumped constant type delay line 6 must be used to correct the delay of the chrominance signal with respect to the luminance signal. This is because, while other circuit configurations are highly integrated and easy to design, the use of the delay line 6 precludes integration, and it is cumbersome to set constants to obtain predetermined delay characteristics. There were drawbacks such as difficulty in aligning delay characteristics. Further, such a delay line 6 also had a problem in that its phase characteristics were not good.

This invention was made in view of the above points,
It is an object of the present invention to provide a delay processing circuit that uses a charge transfer element as a delay circuit, can obtain an arbitrary delay time by changing a DC voltage, and is suitable for integration.

Examples of the delay processing circuit of the present invention applied to a color television receiver are shown in Figures 3 and 4 below.
This will be explained with reference to the figures.

In FIG. 3, the composite video signal from the video signal amplification circuit 3 is passed through a comb filter 16 so that a luminance signal is obtained as the output of the adder 12, and a carrier color signal is obtained as the output of the subtracter 14. It's summery. The adder 12 is connected to one input end of the adder 20 via a luminance signal delay circuit 30 and a low-pass filter 19, and the subtracter 14 is connected to the color signal output end 8' via a band adjustment circuit 5. . The subtracter 14 also includes a delay circuit 31 and a low-pass filter 21.
is connected to the other input terminal of the adder 20 via the
I am trying to supply it to 0.

The delay circuit 30 is supplied with a transfer pulse from the clock generator 17 and is also applied with a DC voltage V ₁ from a terminal 32, and this delay circuit 30 delays the luminance signal by a time τ ₂ . Furthermore, the delay circuit 31 is supplied with the transfer pulse and is also applied with the DC voltage V ₂ from the terminal 33, thereby delaying the output of the subtracter 14 by a time (τ ₂ −τ ₁ ). In the above, the time τ ₁ is determined by the low-pass filter 21.
This corresponds to the delay time of the VD signal, and the time τ ₂ corresponds to the delay time of the carrier color signal by the band adjustment circuit 5.

With this configuration, the output luminance signal of the adder 12 is delayed by τ ₂ by the delay circuit 30. On the other hand, the VD signal is output by the delay circuit 31 (τ ₂ −τ ₁ )
The total delay time is (τ ₂ - _{τ 1 )} +
τ ₁ =τ ₂ , and the delay of the VD signal with respect to the luminance signal can be compensated for. Furthermore, since the output of the adder 20 is delayed by τ ₂ , it matches the delay time τ ₂ caused by the carrier color signal passing through the band adjustment circuit 5, and the delay of the carrier color signal with respect to the luminance signal can also be compensated. .

FIG. 4 is a modification of FIG. 3, and the same components as those in FIG. 3 are given the same reference numerals. The terminal 34 is the input terminal of the composite video signal, and the luminance signal appearing on the adder 12 side of the comb filter 16 is delayed by the time (τ ₂ −τ ₁ ) by the delay circuit 30A, and The carrier color signal is sent to the delay circuit 31A.
Similarly, it is delayed by (τ ₂ −τ ₁ ). Further, the output of the delay circuit 30A is delayed by a time τ ₁ by the delay circuit 30B, and is supplied to the low-pass filter 19. In addition, the delay circuit 30A and the delay circuit 31
A predetermined DC voltage is applied to the delay circuit 30B from the terminal 35A, and a DC voltage is applied to the delay circuit 30B from the terminal 35B. The rest of the configuration in FIG. 4 is the same as in FIG. 3, and in this FIG. 4 as well, it is possible to compensate for the delay of the VD signal with respect to the luminance signal and the delay of the carrier color signal can.

Next, the delay circuits 30, 3 which constitute the characteristic part of the present invention
1, 30A, 31A, and 30B will be explained with reference to FIGS. 5 and 6. These delay circuits can arbitrarily set the delay time by controlling the DC voltage, and are composed of a delay element using a charge transfer element and a delay time switching circuit.

First, FIG. 5 mainly shows the delay elements, in which an input signal to be delayed is supplied to the terminal 36, and this signal is transferred to the m-bit charge transfer elements CD ₁ to CD _n
A transfer pulse is supplied to the element CD ₁ for the first bit of the delay element consisting of the charge transfer elements CD ₁ to _{CD n} , respectively.
The signal delayed by the first bit is output to terminal ₃₇₁ ,
The second bit delayed signal is output to terminal ₃₇₂ ,
Similarly, the m-th bit delayed signal is sent to the terminal 37m.
is output to.

These terminals 37 ₁ to 37 m are connected in parallel to a delay time switching circuit 38 , and this circuit 38 selects one of the signals obtained at each terminal 37 ₁ to 37 m and outputs it to the output terminal 39 . The signal to be selected depends on the magnitude of the DC voltage supplied to terminal 40. In addition, in FIGS. 3 and 4, the same transfer pulse is supplied to the 1H delay circuit 15, delay circuit 30, and delay circuit 31 that constitute the comb filter 16, but the frequency of this transfer pulse is , it is preferable to set the frequency to an integral multiple of the frequency of the reference subcarrier for demodulating and extracting the color signal from the carrier color signal. By setting like this,
The spectra of the luminance signal and the carrier color signal of the comb filter 16 have characteristics that are more completely separated.

Thus, terminals 32 and 33 in FIG.
By controlling the DC voltage applied to terminals 35A and 35B in the figure, a delayed output having an arbitrary delay time can be obtained. and delay element CD ₁ ~
CD _n is a charge transfer element and can be easily integrated.

Next, a specific example of the delay time switching circuit 38 mentioned above will be explained with reference to FIG.

In FIG. 6, delay signals from delay elements CD ₁ , CD ₂ , CD ₃ are input to terminals 37 ₁ , 37 ₂ , 37 ₃ . Further, the terminal 39 is an output terminal for a delayed signal. Further, the terminal 40 is a DC voltage supply terminal. The configuration of the delay time switching circuit 38 will be described in detail below, focusing mainly on the circuit portion that processes the signal delayed by the second bit (the output signal of the delay element _CD2 ).

Terminal ₃₇₂ is connected to the base of transistor 43, which is connected to transistor 44.
Together with this, a differential amplifier is constructed to amplify the second bit delayed signal. Resistance 45 and 4
6 is connected to form a base bias circuit of transistor 44, and resistor 47 is connected to form a base bias circuit of transistor 44.
3 collector. Resistance 45,4
7 and the collectors of the transistor 44 are connected to the power supply terminal 48, and the collector of the transistor 43 is connected to the base of the output transistor 49. The emitter of this transistor 49 is grounded through a resistor 50, and a delayed signal is output from the emitter to the terminal 39.
Note that the collector of the transistor 49 is connected to the power supply terminal 48.

The collector of a transistor 51 is connected to the common emitters of the transistors 43 and 44, and the transistor 51 is turned on or off depending on the magnitude of the delay time switching DC voltage from the terminal 40. That is, the base of the transistor 51 is connected to the terminal 40, and the emitter of the transistor 51 is connected to the emitter of the paired transistor 52. The transistors 51 and 52 form a differential switching circuit, and the base of the transistor 52 is supplied A switching operation is performed by comparing the reference voltage with the DC voltage at the terminal 40. The above transistor 5
The reference voltage to the base of 2 is the resistor 53, 54, 5
It can be obtained from a voltage divider circuit such as 5. Further, the collector of the transistor 52 is connected to the power supply end 48 via a resistor 56 and to the base of a transistor 57.

The emitter of this transistor 57 is connected to the power supply terminal 48 via a resistor 58, and the collector is connected to the base of a transistor 59B. This transistor 59B is provided in a circuit that processes the delayed signal of the first bit in the preceding stage. still,
The base of this transistor 59B is grounded via a resistor 60B. Also, the transistor 51,
The common emitter of 52 is connected to the collector of transistor 59, whose base is connected to the collector of transistor 57A. This transistor 57A is provided in a circuit that processes the third bit delayed signal. The base of the transistor 59 is grounded via a resistor 60, and the emitter is grounded via a resistor 61.

Note that the circuit for processing the delayed signals of the third bit and the first bit is similar to the processing circuit for the second bit delayed signal described above, and the processing circuit for the third bit delayed signal is designated by the symbol A, and A processing circuit for a 1-bit delayed signal is designated by the symbol B. Note that it is not necessary to provide a transistor equivalent to the transistor 57 in the processing circuit for the first bit delayed signal in the first stage.

The operation of this delayed signal switching circuit 38 is as follows.

First, a case will be described in which a signal delayed by the first bit is selectively output.

Assuming that the reference voltages applied to the transistors 52B, 52, and 52A are Va, Vb, and Vc, respectively, these voltages are sequentially set to different values so that Va<Vb<Vc. In this state, when the voltage applied to the terminal 40 exceeds Va, the transistor 51B is turned on and the transistor 52B is turned off. Therefore, the 1-bit delayed signal supplied to the input terminal ₃₇₁ is amplified by the transistor 43B, and further amplified by the transistor 49B.
B to the output terminal 39. On the other hand, at this time, the next stage transistor 51 is turned off because its base voltage is lower than Vb, and the second bit delay signal is not output, and the transistor 52 is turned on. As a result, the transistor 57 is turned on, supplying a bias to the base of the transistor 59B, and this transistor 59B remains on, and the processing circuit for the first bit delay signal operates, and the first bit delay signal processing circuit operates.
Derivation of the bit delayed signal is performed.

Next, the case of outputting the second bit delayed signal will be explained.

When the DC voltage at the terminal 40 exceeds Vb, the transistor 51 turns on, the transistor 52 turns off, the transistor 51A turns off, and the transistor 52A turns on.
On, transistor 57A turns on, and transistor 59 turns on. Therefore, the second bit delay signal inputted from the terminal ₃₇₂ is transmitted to the transistor 4.
3 and 49 to the output terminal 39. On the other hand, for the first bit delay signal in the previous stage, since the transistor 57 is turned off when the transistor 52 is turned off, the transistor 59B is turned off and the transistor 43B is not operated.
Not derived. Also, since the base voltage of the transistor 51A is lower than Vc for the third bit delay signal,
Since both transistors 51A and 43A are turned off, no signal is drawn out. In addition, at this time, the transistor 5
2A and 57A are turned on, and the transistor 59 remains on. Transistor 57, 57A, 5
7B serves to prevent the operation of the delayed signal processing circuit at the previous stage when deriving the n-th bit delayed signal.

In this way, by setting the DC voltage applied to the terminal 40 to a predetermined value, the delayed signal from the 1st bit to the m-th bit can be arbitrarily selected and output, and the signal delay time can be arbitrarily set. can.

As described above, according to the present invention, it is possible to provide a delay processing circuit that uses a charge transfer element, can set an arbitrary delay time by controlling the DC voltage, and can be easily integrated into an integrated circuit. .

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams showing conventional examples;
FIG. 3 is a block diagram showing an example in which the delay processing circuit according to the present invention is applied to a color television receiver;
Figure 4 is a block diagram showing a modification of Figure 3;
6 is a circuit diagram showing an embodiment of the delay processing circuit of the present invention, and FIG. 6 is a circuit diagram showing an embodiment of the delay time switching circuit in FIG. 30, 30A, 30B, 31, 31A...delay circuit, _CD1 to _CDn ...charge transfer element (delay element),
38... Delay time switching circuit, 39... Signal output terminal, 40... DC voltage supply terminal, 43... Amplifying transistor, 51, 52... Differential switching transistor (comparison means), 53, 54, 55 …
...Voltage dividing resistor (reference voltage supply means), 57... Transistor (pre-stage inoperable means).

Claims (1)

[Claims for Utility Model Registration] (1) A delay processing circuit for outputting an input signal after delaying it with a delay time determined by a change in DC voltage, the circuit for transmitting the input signal at a predetermined frequency. a charge transfer element that is shifted by a pulse and takes out a plurality of parallel outputs each having a different delay time; a plurality of signal amplification means each receiving one of the parallel outputs and having the output connected to a common output terminal; It is connected to each of the amplification means to form multiple stages, each stage is connected to a reference voltage source and a common controllable DC voltage source, and voltages of different values are sequentially supplied as the reference voltage, and each of these reference voltages and control means for operating any one of the signal amplification means when any one of the stages becomes operational by comparison with the DC voltage; and when any one of the stages of the control means is in the operational state; a delay processing circuit comprising means for disabling a preceding stage thereof. (2) A delay processing circuit that delays and outputs an input signal with a delay time determined by changes in DC voltage, which shifts the input signal with a transfer pulse of a predetermined frequency and outputs a signal that is different from each other. A charge transfer element that takes out multiple parallel outputs with a delay time; Consists of an n-stage circuit (n is a positive integer of 2 or more), and each stage circuit shares the emitters of the first and second transistors. a differential amplifier connected to the base of the first transistor, with a controllable DC voltage applied to the base of the first transistor and a reference voltage applied to the base of the second transistor; and a collector-emitter path connected to the collector of the first transistor. Output means includes a third transistor connected to the base of which the input signal is supplied, the input signal being able to be derived from the collector when the first transistor is conductive;
and a current source transistor connected to the common emitter of the first and second transistors, and further includes a current source transistor connected to the common emitter of the first and second transistors, and a circuit of the previous stage when the second transistor of each stage is conductive. Means for preventing conduction of the current source transistors is provided, the reference voltages to the bases of the second transistors in each stage are set to different potentials sequentially, and the outputs from the output means in each stage are connected to a common output terminal. and supplying one of the parallel outputs from the charge transfer blocking circuit to the base of the third transistor of each stage, in response to a change in the DC voltage to the first transistor of each stage. A delay processing circuit according to claim 1, characterized in that the delay processing circuit comprises: a delay time switching circuit configured to derive an output signal from a circuit in any one stage;