JPS6336052U - - Google Patents

Info

Publication number
JPS6336052U
JPS6336052U JP1986129468U JP12946886U JPS6336052U JP S6336052 U JPS6336052 U JP S6336052U JP 1986129468 U JP1986129468 U JP 1986129468U JP 12946886 U JP12946886 U JP 12946886U JP S6336052 U JPS6336052 U JP S6336052U
Authority
JP
Japan
Prior art keywords
motherboard
top surface
logic lsi
chip module
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986129468U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986129468U priority Critical patent/JPS6336052U/ja
Publication of JPS6336052U publication Critical patent/JPS6336052U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Description

【図面の簡単な説明】
第１図は、本考案の実施例の断面図、第２図は
他の実施例の断面図、第３図はさらに他の実施例
の断面図、第４図は従来のマルチチツプモジユー
ルの構成図、第５図、第６図は、本考案の別の実
施例の説明図である。 １……放熱フイン、２……ＲＡＭ、３……チツ
プキヤリア、４……スペーサ、５……セラミツク
基板、６……リードフレーム、７……キヤツプ、
８……論理ＬＳＩ、９……リード。

Claims (1)

    【実用新案登録請求の範囲】
  1. セラミツク基板より成るマザーボード下面に論
    理ＬＳＩを配置し、上述マザーボード上面に複数
    のチツプキヤリア式のＲＡＭを配置したマルチチ
    ツプモジユールにおいて、マザーボード上面のＲ
    ＡＭおよび論理ＬＳＩ配置位置の裏側であるマザ
    ーボード上面に直接接触するように、一体ででき
    た。放熱フインを設けたことを特徴とするマルチ
    チツプモジユール。
JP1986129468U 1986-08-27 1986-08-27 Pending JPS6336052U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986129468U JPS6336052U (ja) 1986-08-27 1986-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986129468U JPS6336052U (ja) 1986-08-27 1986-08-27

Publications (1)

Publication Number Publication Date
JPS6336052U true JPS6336052U (ja) 1988-03-08

Family

ID=31026062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986129468U Pending JPS6336052U (ja) 1986-08-27 1986-08-27

Country Status (1)

Country Link
JP (1) JPS6336052U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373458U (ja) * 1989-11-22 1991-07-24
JPH0613540A (ja) * 1991-12-03 1994-01-21 Nec Corp マルチチップモジュール
WO2008108335A1 (ja) * 2007-03-06 2008-09-12 Nikon Corporation 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373458U (ja) * 1989-11-22 1991-07-24
JPH0613540A (ja) * 1991-12-03 1994-01-21 Nec Corp マルチチップモジュール
WO2008108335A1 (ja) * 2007-03-06 2008-09-12 Nikon Corporation 半導体装置
JP5521546B2 (ja) * 2007-03-06 2014-06-18 株式会社ニコン 半導体装置

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