JPS6339657Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a cycle selection device that automatically obtains a signal synchronized with a specific cycle of a carrier wave of a received Loran pulse in a Loran C receiver.

[Conventional technology]

In Loran C, highly accurate measurements are performed by obtaining not only the phase difference between the pulses from the main station and the slave station, but also the phase difference between the carrier waves of the pulses. In order to obtain this carrier wave phase difference, it is necessary to obtain a signal synchronized with that specific cycle, and therefore it is necessary to select a specific cycle.

In the Loran C system, as shown in FIG. 1A, the Loran pulse Pm from the main station and the Loran pulses Psa and Psb from at least two slave stations forming a chain with the main station are transmitted. The main station pulse Pm is
Consisting of 8 pulses at 1ms intervals followed by one pulse 2ms apart, slave station pulses Psa, Psb
consists of 8 pulses each with an interval of 1 ms.
The envelope of each of these pulses has a shape as shown in FIG. 1B. Furthermore, if a certain phase of the carrier wave of each pulse is + and the opposite phase is -, then the phase of the main station Loran pulse Pm is coded, for example, as shown in Figure 2, and the slave station is coded in the same way. It is possible to select from which station the message is coming from.

Each pulse becomes a carrier wave like signal B in Figure 1, and a point near this third cycle is selected as a specific cycle point for making measurements that are not affected by spatial waves. Measurements are being made while tracking the object.

As this sorting/tracking means,
Create a waveform whose phase inverts at a specific cycle point, and use pulses placed before and after the pulse to track this point at a short interval of 1/4 cycle of the carrier wave. A method is disclosed in which this is performed by determining the appearance status of sampling values.

[Problem to be solved]

In the spaced arrangement as described above, each polarity at the spaced sampling points is reversed at each zero crossing point of the carrier wave, that is, every 1/2 cycle point,
There is a complexity in that the phase is reversed again between the front side and the rear side of the point where the phase was reversed, and it is difficult to simplify the device configuration.Therefore, it is expected to simplify this and provide a device that is inexpensive. There is a problem with that.

[Means for solving problems]

In order to solve the above-mentioned problems, this invention is based on a cycle in which a received pulse signal, that is, signal B in FIG. 1, is shaped into a square wave as shown in FIG. Create a signal and convert this cycle signal into the tracking pulse P ₁ shown in Figure 1E.
The tracking pulse _P1 is controlled by the sampling output so that the pulse coincides with the zero-crossing position of the cycle signal (in the figure, the falling zero-crossing position in the figure). Furthermore, in order to select a specific cycle of the rising edge of each pulse, FIG.
As shown in FIG. 2, for example, a so-called envelope signal in which the phase of the carrier wave is inverted at the third rising cycle is obtained.

In other words, a square wave signal is created in which a short period square wave with one cycle being 1/2 the period of the carrier wave is provided at the third cycle.

Since the period of the current Loran C carrier wave is 10 μs, this short period corresponds to 5 μs.

Then, as shown in FIGS. 1F and 1G, the antinode part of the square wave that precedes the tracking pulse P ₁ , for example, the pulse P ₂ located at a time 1/4 of the period of the carrier wave earlier. and the antinode of the square wave that follows the tracking pulse P ₁ , for example, the pulse P ₃ located at a time 3/4 of the period of the carrier wave.
The arrangement is selected so that the polarities obtained by sampling the envelope signal D using these pulses are positive on one side and negative on the other.

As mentioned earlier, the phase of the carrier wave of the Loran pulse is encoded as shown in Figure 2, but
This code is decoded to obtain an envelope signal with a constant phase.

Therefore, for example, the phase is always set to + before a fixed cycle and - after it. Integrate the output of sampling the envelope signal with either envelope sample pulse P ₂ or P ₃ , and if the integral output is, for example, positive, select envelope sampling pulse P ₃ , thereby sampling the envelope signal, Integrate its output and if it is negative then select envelope pulse P ₂ . In this way, if positive and negative values are obtained alternately as integral outputs, correct tracking is performed.In other words, the tracking pulse tracks the zero crossing point of the falling edge of the specific cycle of each pulse, in this example, the third cycle. I understand. In the above control, for example, if the integral output is positive and then the envelope sampling pulse
If the output of the integrating circuit is positive again even if the envelope signal is sampled by pulse P ₃ with a certain phase delay with respect to P ₂ , then the envelope signal D and each sampling pulse P ₂ , P in Fig. 2 ₃ , the tracking pulse P ₁ is ahead of the specific cycle of the Loran pulse carrier wave. Conversely, if the output of the integrating circuit is negative, the next pulse P ₂
is selected, but if the integral output is negative even after that, the tracking pulse _P1 is delayed from the specific cycle. Because of this relationship, if the output of the integrating circuit has the same polarity twice, the phase of the tracking pulse P ₁ and, along with this, the phases of the envelope sampling pulses P ₂ and P ₃ are simultaneously controlled for tracking. Pulse P ₁ tracks a specific cycle,
The envelope sampling pulses P ₂ and P ₃ are automatically controlled to be positioned before and after a specific cycle.

〔Example〕

Examples will be described below with reference to the drawings.

In FIG. 3, a Loran signal received from an antenna 11 is amplified by a preamplifier 12, and the amplified output is shaped into a square wave by a carrier wave in a cycle signal circuit 13 as shown in FIG. 1C. . This output is converted by a cycle decoder 14 into a cycle signal of a carrier wave in which each pulse has the same phase. This cycle signal is sampled in the tracking sampling circuit 15 by the tracking pulse P ₁ from the frequency dividing circuit 16, and depending on whether the sampling result is positive or negative, the shift circuit 17 is controlled. Circuit 16
The phase of the tracking pulse P1 is controlled by controlling the frequency division ratio of the tracking pulse _P1 , whereby the tracking pulse _P1 is controlled to track the zero crossing point of the falling edge of a specific cycle of the cycle signal, for example, the third cycle. Ru. Frequency divider circuit 16 divides the stable clock signal from reference oscillator 18. The frequency of the oscillator 18 is selected to be, for example, 1 MHz or 10 MHz depending on the required measurement accuracy.

On the other hand, a part of the output of the preamplifier 12 is branched and supplied to the envelope signal generation circuit 19.
The envelope signal generation circuit 19 generates a signal whose phase is reversed in a specific cycle of the carrier wave in the rising part. For example, the received signal is
In other words, if you combine a carrier wave delayed by half a period of the carrier wave and a non-delayed wave, and in that case, adjust the amplitudes of both so that they are equal in a specific cycle, a signal whose phase is inverted at the point where the amplitudes become equal, is obtained. In other words, an envelope signal is obtained. This is also output as a square wave as shown in FIG. 1D. This envelope signal is converted into a constant phase by an envelope decoder 21 regardless of the phase code of each pulse shown in FIG. Note that the envelope decoder 21 and cycle decoder 14 are connected to the decode pulse generation circuit 2.
The control signal of the decode pulse generation circuit 22 is generated from the output of the frequency divider circuit 16, and the signal detection circuit 20 generates a control signal from the output of the cycle signal generation circuit 13. The local Loran pulse is detected and the frequency dividing circuit 16 is synchronized by the detected output. The envelope signal as shown in FIG.
Envelope sample pulse from 4 P ₂ or
Sampled by P ₃ . The sampled output, which is a positive or negative output as seen from the relationship between D, F, and G in FIG. 1, is integrated in an integrating circuit 25. This integration eliminates errors due to waveform disturbances, such as when the signal to noise ratio of the Loran reception signal is poor and the output from the envelope sampling circuit 23, which should originally be a positive pulse, sometimes changes to a negative pulse. When the output of the integrating circuit 25 exceeds a predetermined value in the positive direction, the integrating circuit 25 is reset and the cycle selection circuit 26 is controlled, and its output causes the envelope pulse switching circuit 24 to output a tracking pulse as described above. Pulse P ₃ delayed from P ₁ is selected, and sampling by the envelope sampling circuit 23 is thereby performed. As a result, the sampling output becomes negative, and when the output of the integrating circuit 25 exceeds a predetermined value in the negative direction, the cycle selection circuit 26 selects an envelope sampling pulse P ₂ that is more advanced than the tracking pulse from the envelope pulse switching circuit 24.
And the integrating circuit 25 is reset. In this way, when the tracking pulse P ₁ is located at a particular cycle of the received pulse, the envelope sampling pulse
P ₂ and P ₃ are alternately supplied to the envelope sampling circuit 23. However, as mentioned above, if one of the pulses P ₂ or P ₃ is selected consecutively, that is, the output of the integrating circuit 25 exceeds a predetermined value twice in the same direction, the shift command signal is sent from the cycle selection circuit 26. is emitted, the shift circuit 17 is controlled,
As described above, the frequency divider circuit 16 is controlled by the shift circuit 17 to advance or delay the tracking pulse _P1 by a certain phase. When the tracking pulse P ₁ is controlled in this manner, the phases of the envelope sampling pulses P ₂ and P ₃ also change accordingly. This kind of action is repeated,
Finally, the tracking pulse P ₁ coincides with a specific cycle of the Loran pulse, and the output of the integrating circuit 25 exceeds a certain value in the opposite direction, which is repeated alternately, that is, the envelope sampling pulses P ₂ and P ₃ are alternately selected. A specific cycle is selected.

In the envelope pulse switching circuit 24,
Envelope sampling pulses P ₂ and P ₃ are generated by the envelope pulse generation circuit 27 based on the signal from the frequency dividing circuit 16, that is, the pulse P 2 is a certain phase advanced with respect to the tracking pulse P ₁ , and the other is a certain phase lag behind the tracking pulse P ₁ . One of the pulses P ₃ is selected by the output of the cycle selection circuit 26. In addition, the cycle selection circuit 2
The timer 28 is reset every time a shift command pulse is obtained from 6, and when the timer 28 has elapsed for a predetermined period of time, the timer output causes the display 2 to be reset.
9 is driven, and it is displayed that the detection of the specific cycle has been completed.

Next, a specific example of the integration circuit 25, cycle selection circuit 26, etc. will be explained with reference to FIG. The integration circuit 25 performs integration digitally, and is provided with an up-down counter 31. Every time a carry or carry-down output is obtained from the up-down counter 31, a signal is applied to the load terminal 32 of the up-down counter 31. A value from the circuit 33, for example, a value half the maximum count value of the up-down counter 31, is set in the up-down counter 31. By the pulse from the envelope pulse switching circuit 24,
In the envelope sample circuit 23 consisting of a flip-flop circuit, an envelope decoder 2
1 is sampled, and depending on whether the sampling output is positive or negative, the up-down counter 31 is controlled to be in an up-count state or a down-count state, and at the same time, an envelope sampling pulse signal _P2 or P2 is controlled. ₃ is slightly delayed by the delay circuit 30 and supplied to the up-down counter 31 as a clock pulse.

In this way, when the positive pulse output from the sampling circuit 23 exceeds a predetermined number, a carry is output from the up-down counter 31, and conversely, when the negative pulse output exceeds a predetermined number, a carry is output. As mentioned above, the set value of the setting circuit 33 is set in the counter 31 by the output thereof, and this is also applied as a clock to the flip-flop 34 constituting the storage circuit, and the state of the output of the sampling circuit 23 at that time is stored. be done. That is, whether it is positive or negative is stored in the flip-flop 34. The mutually opposite phase terminals of this flip-flop 34 are connected to a gate 35 in the envelope pulse switching circuit 24,
36 respectively. These gates 3
5 and 36, a pulse P 2 that is a certain phase ahead of the tracking pulse P ₁ obtained by dividing the pulse from the frequency dividing circuit 16, and a pulse that is a certain phase behind the tracking pulse P ₁ .
P ₃ is generated and supplied by pulse generation circuits 37 and 38, respectively. If the value read into the output of flip-flop 34 is positive, gate 36 is opened and envelope sampling pulse _P3 passes through gate 36 and is outputted through OR gate 39 as an envelope sampling pulse. Conversely, when a negative value is read into the flip-flop 34, the gate 35 is opened and the envelope sampling pulse _P2 passes through the gate 35.
Furthermore, it is obtained as an envelope sampling pulse through an OR gate 39.

The output of the flip-flop 34 is read into the flip-flop 41 using the carry-up or carry-down output of the up-down counter 31 as a clock. The respective Q output sides of the flip-flops 34 and 41 are logically ANDed in an AND circuit 42, and the respective outputs are logically ANDed in an AND circuit 43. Therefore, for example, the up-down counter 31 carries up twice, the Q outputs of the flip-flops 34 and 41 become logic "1", and an output is provided to the AND circuit 42, which drives the one-shot multivibrator 44. Ru. This output causes the tracking pulse _P1 to be set at a constant phase (10 μs) in the shift circuit 17.
A delaying signal is generated. When the up-down counter 31 generates two consecutive down-digit pulses, the outputs of the flip-flops 34 and 41 become logic "1", and an output is obtained from the AND circuit 23, which drives the one-shot multivibrator 44, which More shift circuit 17
is controlled to advance the tracking pulse _P1 by 10 μs.

Each output pulse of the one-shot multivibrators 44, 45 is also supplied to a gate 46, and this output is supplied to a timer 28 as a reset pulse. Timer 28 counts the clocks from terminal 47 and sets flip-flop 48 when this exceeds a predetermined value. Flip-flop 48 is reset in advance by a signal from terminal 49 at startup. When the flip-flop 48 is set, its output causes an indicator 29 to appear indicating that a particular cycle has been selected.

As described above, the specific cycle selection device according to this invention automatically selects a specific cycle. In that case, it is said that by using the integrating circuit 25, the Loran C can be used even when the SN ratio is poor, and it is possible to correctly select a specific cycle even when the SN ratio is poor. Moreover, when the output of the integrating circuit exceeds a predetermined value multiple times in the same direction, the tracking pulse is controlled to move by the carrier wave period, so there is no risk of the tracking pulse being moved by mistake, and from this point of view, the SN ratio is also improved. Even in the worst case, a specific cycle can be selected in a short time.
That is, for example, if the setting value of the setting circuit 33 in the integrating circuit 25 is doubled and an output is obtained from the integrating circuit 25, it is possible to control the shift circuit 17 according to the output at that time, but the noise pulse Since it occurs randomly, it is better to control the shift circuit 17 when the integral output occurs twice in the same direction as in the embodiment shown in FIG. 4, since it is less affected by noise.
Judgment accuracy increases. In other words, in the case of the same judgment accuracy, the set value can be reduced to one-half or less compared to the case where the shift circuit is controlled by one integral output, and the measurement time can be shortened. In addition, in the above, the interval between the tracking pulse P ₁ and the two envelope sampling pulses P ₂ and P ₃ is one wavelength, that is, 10 μs corresponding to one period of the carrier wave, but even if this interval is made more than one wavelength, , the position of each of these pulses is the antinode of the envelope signal D at the preceding time point and the envelope signal at the following time point when looking at the pulse P ₁ in the state where the pulse P ₁ is at the position E in FIG. 1. It suffices if they are located at the antinodes of D, and these antinodes may be located on either side of the positive or negative polarity.

Further, it goes without saying that the tracking point of the pulse P ₁ can operate in the same manner as described above even if it is at the trailing edge as long as it is at the edge of the 1/2 period cycle wave.

In other words, when the tracking pulse P ₁ selects that particular cycle, even if the sampling outputs of the envelope signal are not necessarily in opposite phases or have the same polarity, one of the outputs will be passed through the inverter. Therefore, it can be operated in the same way. Further, as the integrating circuit 25, an analog integrating circuit may be used. In the explanation of FIG. 3, an example is shown in which a specific cycle is selected for one Loran pulse, but in reality, at least three similar circuits operating in parallel are provided, and the main station and two
A particular cycle of each Loran pulse from the two slaves is selected.

[Effect of idea]

According to this invention, as described above, an envelope signal D is obtained in which a square wave with a short period, where one cycle is 1/2 of the period of the carrier wave, is provided at a specific cycle position of each pulse in the Loran C signal. , the tracking pulse P ₁ at the edge of this short period cycle
A sampling pulse P ₂ ,
Because P ₃ is positioned, the judgment structure of the sampling detection value only needs to be placed at the point where it inverts before and after a specific cycle, which eliminates complex judgment structures such as the judgment structure for each zero cross before and after each 1/2 cycle of the carrier wave. It has the advantage of eliminating the need for any configuration and providing an inexpensive device with fast tracking operation.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram for explaining the cycle selection device for a Loran receiver according to this invention, Fig. 2 is a diagram showing the phase code of the Loran signal, and Fig. 3 is a diagram showing the cycle selection device for a Loran receiver according to this invention. FIG. 4 is a block diagram showing a specific example of an integrating circuit, a cycle selection circuit, an envelope pulse switching circuit, etc. FIG. 13: Cycle signal circuit, 14: Cycle decoder, 15: Tracking sampling circuit, 16: Frequency dividing circuit, 17: Shift circuit, 18: Reference oscillator, 1
9: Envelope signal generation circuit, 21: Envelope decoder, 23: Envelope sample circuit, 24: Envelope pulse switching circuit, 25:
Integration circuit, 26: Cycle selection circuit.

Claims (1)

[Claims for Utility Model Registration] A device for selecting and tracking a specific cycle of a carrier wave in a pulse of a received Loran C pulse signal, comprising: a) a period (hereinafter referred to as T) of the carrier wave at the location of the specific cycle; an envelope signal forming means for outputting a signal obtained by shaping the carrier wave into a square wave as an envelope signal by providing a square wave whose one cycle is 1/2 of the carrier wave (hereinafter referred to as a 1/2 period square wave); b. a tracking pulse means for outputting a pulse for tracking an edge portion of a /2 period square wave as a tracking pulse; c positioning at the abdomen of the square wave of the cycle according to T at a time point preceding the tracking pulse in the envelope signal; a preceding sampling means for outputting a signal obtained by sampling a point (hereinafter referred to as a preceding point) as a preceding sampling signal; trailing sampling means for outputting a signal obtained by sampling a point located on the abdomen of the body (hereinafter referred to as trailing time point) as a trailing sampling signal; e integrating the preceding sampling signal and the trailing sampling signal; tracking detection means for outputting a signal obtained by detecting that the signal obtained from the above is biased toward either the preceding sampling signal side or the following sampling signal side and exceeding a predetermined value as a tracking signal; f A Loran C receiver cycle selection device comprising: tracking means for shifting the timing of the tracking pulse to a point corresponding to T by the tracking signal.