JPS6339990B2 - - Google Patents

Description

[Detailed Description of the Invention] It is widely practiced to convert an analog signal into a coded digital signal and transmit it or record it on a recording medium. If a code error occurs due to a cause, pulse noise will occur in the reproduced output. Therefore, when transmitting or recording, a parity code or cyclic code is attached to the encoded signal and transmitted or recorded, and when decoding, the above-mentioned code is added. Detect code errors using parity codes and cyclic codes,
When an error is detected, for example, the code word in which the error was detected is replaced with the previous code word and the output signal is held, or if the error is only one word, addition is performed. The average value of the preceding and succeeding words was obtained using an instrument, and this was then replaced with the code word in which the error was detected.

However, when the above-mentioned conventional error word correction means has consecutive error words, the former correction means of the above-mentioned conventional method produces a discontinuous reproduced signal waveform, resulting in large correction noise. However, the latter correction means of the conventional method described above had a drawback in that it could not be corrected.

The present invention satisfactorily solves the above-mentioned drawbacks of the conventional method by estimating and interpolating values indicated by error-free code words in the vicinity before and after the code words that contain errors, even if code words with errors occur consecutively. , a code word error correction device having a simple configuration that allows a reproduced output signal with less noise to be obtained, that is, a code word error correction device that writes data in a write period and a read period that are set in synchronization with the sampling period for the original signal. A write address counter and a read address counter send out an address signal and a read address signal, and operate a write address counter and a read address counter that circulate while maintaining a predetermined address interval from each other. A code word is temporarily stored in a memory and output after being delayed by a time corresponding to the predetermined address interval, and a certain code word in the write address counter and the read address counter is
The period from the end of one write period and read period to the start of the next write period is defined as an error correction period. The correcting operation in the correcting device is started by the output of a register having a trigger function to start the correcting device configured to switch and a function to temporarily store the address of the memory where the erroneous code word is stored. , a correction device reads the erroneous code word and the error-free code words in the vicinity before and after it from the memory, and corrects the erroneous code word to a value estimated from the values indicated by the error-free code words in the vicinity before and after it;
Write the corrected codeword to the address location of the erroneous codeword in memory, and write the erroneous codeword to the corrected code before the address of the erroneous codeword is specified by the read address counter. A device for correcting an error in a code word by outputting a corrected code word, and a device for correcting a code word having one or a plurality of consecutive errors as the correction device. The values indicated by error-free code words A and B before and after the interval in which code words A and B exist, respectively.
When the relationships between the differences ΔA and ΔB with the error-free code words before or after are of the same sign, the code words A and B are corrected by linear interpolation, and the differences ΔA and ΔB mentioned above are corrected by linear interpolation. When the relationship between is of opposite sign, the slope corresponding to the case where code word A and code word B described above are connected up to the middle of the continuous interval of erroneous words and the slope of difference ΔA or difference ΔB. The purpose of this invention is to provide a device for correcting errors in code words using a device configured to correct erroneous words by quadratic approximation based on the rate of change obtained by dividing the difference between The specific contents will be clarified below with reference to the attached drawings.

FIG. 1 is a block diagram of one embodiment of a code word error correction apparatus according to the present invention, in which 1 is a switch circuit, 2 is a memory;
3 is an address counter, 4 is a noise address register, 5 is a correction device, 6 is an input terminal, 7 is a clock terminal, and 8 is an output terminal.

At the input terminal 6, for example, an output signal from a digital audio signal reproducing device receives a code word consisting of a total of 16 bits, including a 15-bit code corresponding to the sample value of the audio signal and a 1-bit code representing an error. is given as an input signal D _i in the form

The input signal given to the input terminal 6 described above is
The data is sent to the write gate 11 in the switch circuit 1 and written into the RAM 21 in the memory 2 through the data bus during the write period _Tw when the write pulse W in FIG. 2e is at a low level. That is, the clock terminal 7 receives a clock pulse CK{ having the same repetition frequency (assumed to be 48 KHz in the following explanation) as the repetition frequency of the sampling pulse used to obtain the sample value of the original audio signal. Figure 2a} is given, and the aforementioned clock pulse CK triggers the monostable multivibrator 12 to synchronize with the clock pulse CK as shown in Figure 2c.
The DMAC signal is output from the monostable multivibrator 12, and the monostable multivibrator 13 to which the DMAC signal is given is outputted from the monostable multivibrator 12.
A write pulse W and a read pulse R (FIG. 2f) are sent out during the period when the DMAC signal is at a high level. The write gate 11 and the gate 18 are opened only during the period when the write pulse W described above is at a low level, and the write gate 11 sends the input signal applied to the input terminal 6 to the RAM 21 in the memory 2, and the gate 18 sends the address signal from the address counter 31 to the RAM 21 in the memory 2, and furthermore, the low level write pulse W is sent to the RAM 21 in the memory 2 via the switch 14, so that the input terminal 6 is connected to the RAM 21 during the write period Tw. Since the code word of the input signal sent from the address counter 31 to the RAM 21 through the gate 18 and the address bus is stored in the address position of the RAM 21 corresponding to the address signal being applied to the RAM 21 from the address counter 31 through the gate 18 and the address bus. be.

When the DMAC signal is high level, the switch 14 described above outputs a low level write pulse W.
(R/W), and when the DMAC signal is low level, the CPU 5 in the correction device 5
Outputs the control signal R/W from 1.

During the read period T _R following the write period Tw described above, a low level read pulse R is sent from the monostable multivibrator 13 to open the gates 15 and 19, and during this period, the write pulse W is high. Write gate 11 because it becomes level
and gate 18 are closed, and the switch 14 sends a high-level pulse W to the RAM 21. Therefore, the address signal specified by the address signal sent from the read address counter 32 to the RAM 21 via the gate 19 and the address bus is sent from the switch 14 to the RAM 21. RAM21
The stored contents in the memory are read out, and the read code word is sent to the output terminal 8 via the data bus and the gate 15.

In the write period Tw and read period T _R , the address position of the RAM 21 where the code word is written and the address position of the RAM 21 where the code word is read are set to indicate a predetermined address interval. However, this will be explained next using a specific example. Now, RAM21 (256 words x 16 bits)
It also has a storage capacity of a write address counter 31 and a read address counter 32.
and sends an address signal of 0 to 255 with 8 bits each, and a clock pulse
Considering the case where the CK repetition frequency is 48KHz,
A code word is written to address 0 of the RAM 21 during a certain write period TW, and the storage capacity at address 1 of the RAM 21 is read out during a certain read period _TR in which the end of the above-mentioned certain write period Tw is the start of the read period. If the relationship between successive write periods and read periods is determined, such as, the address position of the RAM 21 where the code word is written,
The address interval from the address position of the RAM 21 where the code word is read is 256, so the time it takes to read the memory content written to a certain address is 256/48 (KHz) ≒ 5.3 (ms). becomes.

In this way, the input signal supplied to the input terminal 6 is written to the RAM 21 in the memory 2, and before it is read out and sent to the output terminal 8, the input signal is input to the write address counter 31 and the read address counter 32. Errors in the code word of the input signal are subject to a time delay corresponding to the predetermined address interval.
It can be sufficiently modified within the time from when it is written to the RAM 21 until when it is read.

The above-mentioned write address counter 31 and read address counter 32 count the pulses of the DMAC signal and rotate while sequentially outputting numerical values from 0 to 255, respectively, but the read address counter 32 makes one cycle when the write address counter 31 goes through the cycle. The output of the write address counter 31 is synchronized with the write address counter 31 by being set by a carry signal (CA signal) that is output every time. , and the output of the read address counter 32 is sent to the gate 19 via the bus RB. Gates 18 and 19 are connected to the bus WB mentioned above.
The address signal being supplied through (RB),
As described above, the gate is opened to send data to the RAM 21 during the write period Tw (read period T _R ).

If there is an error in the code word of the input signal supplied to the input terminal 6, an error code ER indicating the error bit in the 16-bit code word supplied to the input terminal 6 is set.
When the bit goes high, this error code ER
is register 4 in noise address register 4
At the same time, the contents of the write address counter 31 (the first address where the error occurred) are also stored in the register 41.

The register 41 is specified by the output EN of the address encoder 42 that specifies this register 41, and its stored contents are transmitted via the data bus.
After being read by the CPU 51, the stored contents are held until the CPU 51 rewrites the erroneous bits to 0.

In the illustrated example, the correction device 5 includes a CPU 51,
This correction device 5 is shown as a program logic device composed of a ROM 52, a RAM 53, a synchronization circuit 54, a clock circuit 55, etc., and this correction device 5 corrects the code words written in the RAM 21 in the memory 2 described above. The necessary error correction operations are performed during the low level of the DMAC signal so that the erroneous codeword is corrected before being read out and sent to the output terminal 8. The modification device 5 in the illustrated example will be described as having its function under program control of the ROM 52, rather than being activated by a startup device and proceeding to an interrupt routine. Ru.

That is, the modification device 5 in the illustrated example has a ROM 5
register 41 in the noise address register 4 according to the program stored in the noise address register 2.
The stored contents of are read into the accumulator of the CPU 51 by specifying the address encoder 42, and when the bit of the error code ER stored in the register 41 is at a high level, the stored address value is read.
Write to RAM53 and set the error code ER bit to 0.
When the correction is completed, the address encoder 42 is designated again and the error is waited for.

In the correction device 5, when the DMAC signal is at a high level, this signal prevents the address bus terminal and data bus terminal of the CPU 51 from losing control.
RAM21 in memory 2 is write gate 1
1, gate 15, and gates 18 and 19. In this way, when the DMAC signal is at a high level, the clock circuit 55 operates as follows.
The output clock φ of the synchronizing circuit 54 is temporarily extended as shown in FIG.
1 is suspended, and when the DMAC signal returns to the low level again, the CPU 51 is made to continue the operation.

The error correction method for an erroneous code word in the correction device 5 is based on the ROM 5 provided in the correction device 5.
It goes without saying that this can be changed by changing the program that should be stored in 2.
Next, a case will be described in which an erroneous code word is corrected according to a program example as shown in the flowchart of FIG.

In the flowchart shown in Figure 3, the program starts from step (1) and starts again from step (12).
It shows a program that loops back to (1) and corrects erroneous words by linearly interpolating them between non-erroneous words.

First, in step (1), the contents of register 41 are
The CPU reads it (loads it to the accumulator using the load instruction) and checks whether there is an error bit in step (2) (loads the error bit into the most significant bit, sends it to the carry using the left shift instruction, and performs a conditional branch using the carry). If there is an error, perform the correction process from step (3) onwards, and if there is no error, return to step (1).

In step (3), the address of the read code word containing the error is stored (after shifting the accumulator to the right and returning the contents, it is loaded into the index register and also stored into the RAM 53). Step (4) is a wait for a period of time so that the correction process can be performed after the erroneous codeword and the subsequent non-erroneous codeword have been written (loading a constant number, In step (5), the contents of RAM 21 in memory 2 are loaded using the same operation as in step (1), and then the contents are placed at the bottom. Examine the erroneous bits by right-shifting,
Addresses are specified in order by index qualification,
Obtain the number C of consecutive errors. At this time, the error bit of the code word containing the error is set to 0 so that it is not calculated. In step (6), the values A and B of the code words before and after the erroneous code word are loaded into the accumulator, and the difference BA=S is obtained by a subtraction instruction.

Furthermore, in step (7), divide S by (C+1),
Obtain the difference D. Then, in step (8), the erroneous code words are stored in the address locations in the form (A+D), (A+2D), . . . and replaced with code words of corrected values.

In steps (9) to (11), in order to search for code words with errors that may have been written after this, the same operation as in step (5) described above is performed, and if the error bit is 1, If not, repeat step (9) without specifying the RAM 21 address one cycle while comparing the address obtained in step (1). If an error is found, proceed to step (5) and make the corrections described above. Processing is performed in steps (5) to (8). If there is no error after going through one cycle in step (11), register 41 is returned in step (12).
The error bit is reset by the store instruction and the process returns to step (1).

By performing such a correction process, an erroneous word can be corrected by linear interpolation from the values of the code words before and after the word, and as a result, a signal from which reproduced sound with less noise can be obtained can be obtained.

FIG. 4 is a waveform diagram showing an example of waveforms when correction is performed according to the program shown in the flowchart shown in FIG. is the original signal waveform, the white circles in Figure 4a are the sample values of the reproduced output, and the white circles in Figure 4b are the values of the code words before and after the erroneous code word. The results are shown when the results are corrected by linear interpolation.

As is clear from the waveform diagrams shown in Figures 4a and b, the correction of the part α in the figure is good, but the correction of the part β in the figure causes a large error with respect to the original signal. It has become a thing.

The flowchart in FIG. 5 uses the previously described method to improve the method of correcting erroneous code words compared to linear interpolation so that the correction of the part β in FIG. 4 is in a good state. 3 shows a flowchart in which some of the steps in the flowchart shown in FIG. The result is shown when a certain codeword is modified.

In steps (13) to (16) in the flowchart shown in FIG. 5, step (13) is the same as step (7) in the flowchart shown in FIG.
, and if the difference in value between codeword A and the correct codeword immediately before this codeword A is ΔA, and the difference in value between codeword B and the correct codeword immediately after this codeword B is ΔB, then In this step (13), the difference Δ and the difference ΔB are obtained and given to the next step (14), and in the step (14), when the difference Δ and the difference ΔB have the same sign, the flowchart shown in the third figure described above is applied. Continue to step (8) in the middle, and if the difference Δ and the difference ΔB have different signs, continue to step (15). Step 15
Then, from the number of errors C and the difference D between B and A, ΔΔ=(D−Δ)/{[(C+1)/2]+1} is obtained. In the above equation, [ ] is a Gauss symbol, and [(C+1)/2] is an integer with the decimal point omitted.

As shown in Figure 7a and b, ΔΔ is calculated by dividing the difference (X ₁ −A), ( X ₂ −
X ₁ )... changes by a constant value ΔΔ, and from the middle point onward returns from the middle point to the front. X _i (i=1,
2...[C/2]) Take the line so that it is parallel to line AB.

Next, in step (16), the _estimated values X ₁ =A ₊ D+ΔΔ, X ₂ =X ₁ + _D +2ΔΔ _... )/(C+1)... by the code word with the error, and the third
Proceed to step (9) of the illustrated flowchart. The steps after step (9) are the same as in the case of FIG. 3 described above.

The reason for moving to step (8) when the signs of Δ and ΔB are equal in step (14) is that in this case, a waveform with higher likelihood can be obtained by linear interpolation.

Figure 8 shows the case of the conventional prior value hold method (the curve in Figure 8) and the case of the linear approximation (the curve in Figure 8), with the signal frequency on the horizontal axis and the magnitude of the noise on the vertical axis. FIG. 8 is a curve diagram showing the audible evaluation results in the case of a combination of quadratic approximation and linear approximation (curve in FIG. 8); FIG.

As is clear from the above detailed explanation, in the code word error correction device of the present invention, consecutive errors can be corrected by not only single errors but also error-free code words before and near an erroneous code word. According to the present invention, by simply using an error detection code, almost no noise due to errors is detected. Such corrections can be realized by a device with a simple configuration, and according to the present invention, there is no reduction in efficiency due to addition of a code for error correction, reduction in efficiency due to double recording, and cost of the correction device. This has the advantage of being able to prevent a rise in

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the apparatus for correcting codeword errors of the present invention; FIGS. 2a-f
The figure is a waveform diagram for explaining the operation, FIGS. 3 and 5 are flowcharts, FIGS. 8
The figure is a curve diagram showing auditory evaluation. DESCRIPTION OF SYMBOLS 1... Switch circuit, 2... Memory, 3... Address counter, 4... Noise address register, 5... Correction device.

Claims (1)

[Scope of Claims] 1. A write address signal and a read address signal are respectively sent during a write period and a read period that are set in synchronization with the sampling period for the original signal, and each address is set to a predetermined address. By the operation of the write address counter and the read address counter, which are configured to cycle while maintaining the interval, successive input code words are temporarily stored in the memory and correspond to the predetermined address interval. from the time when one write period and read period in the write address counter and read address counter end to the time when the next write period starts. The error correction period is set as an error correction period, and a trigger function is provided to activate a correction device in which the error correction logic is switched according to the variation of the input signal in response to an error occurrence detection signal. A correction operation is started in the correction device by the output of a register having a function of temporarily storing the stored memory address, and the correction device stores the error code word and the error-free code words in the vicinity before and after it in the memory. Correct the erroneous code word to a value estimated from the values of the error-free code words in its vicinity, write the corrected code word to the address position of the erroneous code word in memory, and read it. Before the address of the erroneous code word is designated by the address counter, the erroneous code word is made into a corrected code word, and the corrected code word is output. A device for correcting codeword errors. 2. As a correction device, the values indicated by error-free code words A and B before and after the interval in which one or several consecutive erroneous code words exist, and the values before code words A and B. Or, if the relationships between the differences ΔA and ΔB with the later error-free codewords are of the same sign, the codewords A and B are corrected by linear interpolation, and the relationship with the differences ΔA and ΔB described above is corrected by linear interpolation. If they have different signs, the number of erroneous words up to the middle of the continuous interval will be the same as code word A and code word B.
A patent claim using a device configured to correct an erroneous word by quadratic approximation based on a rate of change obtained by dividing the difference between the slope corresponding to when connecting the difference ΔA or the slope of the difference ΔB A device for correcting errors in code words according to scope 1.