JPS6342170A - Signal-charge detecting circuit of charge transfer device - Google Patents

Signal-charge detecting circuit of charge transfer device

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Publication number
JPS6342170A
JPS6342170A JP18641586A JP18641586A JPS6342170A JP S6342170 A JPS6342170 A JP S6342170A JP 18641586 A JP18641586 A JP 18641586A JP 18641586 A JP18641586 A JP 18641586A JP S6342170 A JPS6342170 A JP S6342170A
Authority
JP
Japan
Prior art keywords
diffused layer
diffusion layer
floating
floating diffusion
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18641586A
Other languages
Japanese (ja)
Inventor
Kazuo Miwata
三輪田 和雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18641586A priority Critical patent/JPS6342170A/en
Publication of JPS6342170A publication Critical patent/JPS6342170A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate reset noises even if thermal noises are present in a reset transistor, by setting the concentration, the junction depth and the drain voltage of a floating diffused layer so that the floating diffused layer can be completely depleted. CONSTITUTION:In this circuit, the following parts are included: a floating diffused layer 11; a reset transistor 3, which absorbs all the signal charges in the diffused layer 11; and a source follower circuit, which detects the potential change in the floating diffused layer 11. The concentration of the floating diffused layer 11 and a reset drain voltage VRD are set so that the signal charges in the floating diffused layer 11 can be completely absorbed and the floating diffused layer 11 is completely depleted when the reset transistor 3 is conducted. Namely, the floating diffused layer 11 is not an ordinary high concentration N<+> diffused layer but a low concentration N<-> diffused layer. Therefore, the depletion layer is expanded to the side of the floating diffused layer 11 at a P-N junction between a P-type substrate 10 and the floating diffused layer 11. Thus reset noises are reduced, and a high S/N ratio is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電荷転送装置の信号電荷検出回路に関し、特に
その高S/N化に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a signal charge detection circuit for a charge transfer device, and particularly to increasing the S/N thereof.

〔従来の技術〕[Conventional technology]

、1lll近ccD(チャージ・カップルド・デバイス
)素子などき用いた電荷転送装置の利用が活発でおる。
Charge transfer devices using CCD (charge coupled device) elements are being actively used.

例えば、半導体撮像装置などでは既に旧来の電子撮像管
の利用分野を大きく侵食しつつある。
For example, semiconductor imaging devices and the like are already significantly encroaching on the field of use of conventional electronic imaging tubes.

しかしながら%電荷転送装置の信号電荷量はきわめて微
小であるので、この検出回路機能の良否が電荷転送装置
を用い7t!子装置の特性を大きく左右する。
However, since the signal charge amount of the charge transfer device is extremely small, the quality of the detection circuit function depends on the 7t!% charge transfer device. It greatly influences the characteristics of the child device.

第3図は従来の電荷転送装置における信号電荷検出方法
の一つでおる浮遊拡散層を使った電荷検出回路(FDA
)の略図である。CCDは埋込チャンネル型で、P型の
基板10にN型ウェル領域8t″有し、その内に障壁領
域となるP イオン注入層9を有している。FDAはC
ODの最終段にあシ、浮遊拡散層1とMOSトランジス
タ2のゲート容量および配線容量による合成容iCを充
電して、その電位変化全出力するものであり、その動作
を第4図の第3図に対応するポテンシャル図を用いて説
明する。時刻tx  (第4図(a))に、すセットト
ランジスタ3のゲートに高レベルを印力口してリセット
トランジスタ3を導通式せ、浮遊拡散層1の電位VFD
t−リセットドレインの電位VRDと同一とする。つぎ
に、リセットトランジスタ3のゲートに低レベルを印加
してリセットトランジスタ3を遮断状態とじ几後に、時
刻tz  (第4図(b)においてゲートOG5の直前
のCCD 転送ゲート6の下のポテンシャル井戸に蓄積
されてい比信号電荷Qを浮遊拡散層1に流入させる。こ
の信号電荷の流入による浮遊拡散層の電位変化Δ■FD
”MOS)ランジスタ2と抵抗7より成るソースフォロ
ワ−回路で、噴出する。ここで 〔発明が解決しようとする問題点〕 上述しt従来のFDAはリセットトランジスタ3自身の
抵抗の熱雑音の存在のため、リセットトランジスタ3を
遮断する直前の浮遊拡散層lの電位■、D  は高周波
成分が乗っている。このtめ、リセットトランジスタ3
が遮断するたびに、浮遊拡散層の電位VF Dはこの雑
音成分だけ揺らぐ。
Figure 3 shows a charge detection circuit (FDA) using a floating diffusion layer, which is one of the signal charge detection methods in a conventional charge transfer device.
). The CCD is of a buried channel type, and has an N-type well region 8t'' on a P-type substrate 10, and a P ion-implanted layer 9 serving as a barrier region within the CCD.
At the final stage of the OD, a composite capacitor iC consisting of the gate capacitance and wiring capacitance of the floating diffusion layer 1 and the MOS transistor 2 is charged, and the entire potential change is output. This will be explained using a potential diagram corresponding to the figure. At time tx (FIG. 4(a)), a high level is applied to the gate of the reset transistor 3 to make the reset transistor 3 conductive, and the potential VFD of the floating diffusion layer 1 is increased.
It is assumed to be the same as the potential VRD of the t-reset drain. Next, after applying a low level to the gate of the reset transistor 3 to shut off the reset transistor 3, a voltage is applied to the potential well under the CCD transfer gate 6 immediately before the gate OG5 at time tz (in FIG. 4(b)). The accumulated signal charge Q is caused to flow into the floating diffusion layer 1. The potential change of the floating diffusion layer due to the inflow of this signal charge is Δ■FD
The source follower circuit consisting of the ``MOS'' transistor 2 and the resistor 7 erupts.Here, [the problem to be solved by the invention] As mentioned above, the conventional FDA is Therefore, the potentials of the floating diffusion layer l immediately before shutting off the reset transistor 3 have high frequency components.
Each time the floating diffusion layer is interrupted, the potential VFD of the floating diffusion layer fluctuates by this noise component.

これが、いわゆるリセット雑音といわれるものであり、
具体的にはゆらぎの量はkTC(ここでkはポルツマ一
定数、Tは絶対温度)に比列する。
This is what is called reset noise.
Specifically, the amount of fluctuation is proportional to kTC (where k is Portsma's constant and T is absolute temperature).

このリセット雑音はFDAにおいては本質的に存在する
ものであり、従来においては設計上容量Cを小さくする
ことで雑音の低gt行なって米ているが、現在でも電子
数に(11!算して50はどのゆらぎが存在しでおり、
信号電荷賃が少ない時のS/Nは、はぼこのリセット雑
音によって決定ぜ1しているといっても過言ではかい。
This reset noise essentially exists in FDA, and in the past, noise was reduced by reducing the capacitance C in the design, but even now the number of electrons (11! What fluctuations exist in 50?
It is no exaggeration to say that the S/N ratio when the signal charge rate is small is determined entirely by the reset noise.

〔問題点を解決する1cめの手段〕 本発明の電荷検出回路は、浮遊拡散層と、その拡散層内
の信号電荷全すべてすい出すリセットトランジスタと、
浮遊拡散Mの゛−位変化?検出づ−るソース・フォロワ
ー回路とを含む電荷転送装置の信号電荷検出回路におい
て、浮遊拡散層の信号電荷?完全にすい出すことを可能
とする几りに、リセットトランジスタが導通する時に浮
遊拡散層が完全に空乏化することが?rl能となるよう
に浮遊拡散層の濃度とリセットドレイン電圧VRD  
とを設定したことを特徴とする。
[First means for solving the problem] The charge detection circuit of the present invention includes a floating diffusion layer, a reset transistor that drains all the signal charges in the diffusion layer,
Change in the floating diffusion M? In a signal charge detection circuit of a charge transfer device including a source follower circuit for detection, signal charges in a floating diffusion layer? Is it possible for the floating diffusion layer to be completely depleted when the reset transistor is turned on in order to be able to completely deplete it? The concentration of the floating diffusion layer and the reset drain voltage VRD are adjusted so that the rl function is achieved.
It is characterized by setting the following.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.

従来の実施例と異なる点は浮遊拡散層11が通常の濃度
の高いN+拡散層ではなく、濃度の低いN−の拡散層で
ある点である。このように浮遊拡散層11をN−とする
ことによりP型の基板10と浮遊拡散層11との間のP
−N接合において空乏層は浮遊拡散層11の側にも広が
る。よって、浮遊拡散層11のm度と、その深さXJ、
及びそのバイアス電圧によシ、浮遊拡散層11は完全に
空乏化することが可能である。具体的に述べるならは、
NDを浮遊拡散層11のへ一型のドナー製置、NAiP
型基板10のアクセプター磯波、浮遊拡散層11とP型
基板10との接合を階段接合し、逆バイアス電圧t V
 t とし、拡散電位をφとすると、と表わさ詐る。こ
こで851はSi基板の比誘電率。
The difference from the conventional embodiment is that the floating diffusion layer 11 is not the usual high concentration N+ diffusion layer but a low concentration N- diffusion layer. By setting the floating diffusion layer 11 to N- in this way, the P type between the P type substrate 10 and the floating diffusion layer 11 is reduced.
In the −N junction, the depletion layer also extends to the floating diffusion layer 11 side. Therefore, m degrees of the floating diffusion layer 11 and its depth XJ,
Depending on the bias voltage, the floating diffusion layer 11 can be completely depleted. To be specific,
ND is placed in the floating diffusion layer 11 as a type of donor, NAiP
The acceptor wave of the type substrate 10, the junction between the floating diffusion layer 11 and the P type substrate 10 is step-junctioned, and a reverse bias voltage tV is applied.
t and the diffusion potential is φ, it can be expressed as. Here, 851 is the relative dielectric constant of the Si substrate.

g@は真空の銹電軍、qは電子の電荷量、kはボルツマ
ン定数である。
g@ is the vacuum electric force, q is the charge amount of the electron, and k is the Boltzmann constant.

具体的数値を上げるならは、N1=10 ” 5crn
−3゜Xj=LO#m、ND=3X10  Cm   
とするとX(IXIO−’)2 =9.03V =0.603V であるため、逆バイアス電圧として、&4■の印加があ
れば浮遊拡散層11は完全に空乏化する。
If you want to increase the specific value, N1=10” 5crn
-3゜Xj=LO#m, ND=3X10 Cm
Then, X(IXIO-')2 = 9.03V = 0.603V. Therefore, if a reverse bias voltage of &4 is applied, the floating diffusion layer 11 is completely depleted.

完全に空乏化した後では、空乏層の広がルはとまリ、ひ
いては浮遊拡散層11の電位は9.03 Vより変化し
ない。
After complete depletion, the expansion of the depletion layer stops and the potential of the floating diffusion layer 11 does not change below 9.03V.

このように例んは9.03 Vで完全に空乏化すること
ができるN−1全浮遊拡散層11に用いることにより、
リセット雑音?皆無にできることを第2図(alお工び
(b)のポテンシャル図を用いて説明する。時刻ts 
 (第2図(a))にリセットトランジスタ3のゲー)
K高レベルを印加してリセットトランジスタ3を導通芒
せ、浮遊拡散層11内のキャリアをすべて出してしまう
。この時、浮遊拡散層11は9.03 Vにおいて完全
に空乏化するので、それ以上電位変化も起きない。
For example, by using the N-1 floating diffusion layer 11 which can be completely depleted at 9.03 V,
Reset noise? Using the potential diagram in Figure 2 (al work (b)), we will explain what can be done without any problems.
(Figure 2(a) shows the gate of reset transistor 3)
By applying a high level K, the reset transistor 3 is made conductive, and all the carriers in the floating diffusion layer 11 are taken out. At this time, the floating diffusion layer 11 is completely depleted at 9.03 V, so no further change in potential occurs.

この完全空乏化による電位9.03Vは、リセットトラ
ンジスタ3に熱雑音が存在していても、リセットトラン
ジスタ3下のチャネルポテンシャルが9.03 Vに対
して十分深く、リセットドレイン4の電位vILD  
も十分高は詐ば、リセットトランジスj13の熱雑音に
関係なく、リセットごとにかならず9.03 Vに浮遊
拡散Ni111はセットされる。
This potential of 9.03 V due to complete depletion is sufficiently deep compared to the channel potential under the reset transistor 3 of 9.03 V even if there is thermal noise in the reset transistor 3, and the potential of the reset drain 4 vILD
If the voltage is sufficiently high, the floating diffusion Ni 111 is always set to 9.03 V at every reset, regardless of the thermal noise of the reset transistor j13.

すなわち、浮遊拡散層11の電位のゆらぎは起きない。That is, the potential of the floating diffusion layer 11 does not fluctuate.

このゆらぎのない状態で時刻tz第2図(blに信号電
荷全浮遊拡散層11に流入妊ぜ、その電位変化iM(J
Sトランジスタ2と負荷抵抗7とのソースフォロワ−回
路で検出する定め、リセット雑音はリセットトランジス
タ3に熱雑音が存在していても、皆無とすることができ
る。
In this state without fluctuation, at time tz (bl), the signal charge flows into the entire floating diffusion layer 11, and its potential changes iM(J
The reset noise detected by the source follower circuit of the S transistor 2 and the load resistor 7 can be completely eliminated even if thermal noise is present in the reset transistor 3.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、不発明は、浮遊拡散層が完全に空
乏化できるように、その端麗、接合深さ、及びドレイン
電圧全設定することにより、リセットトランジスタに熱
雑音が存在していても、リセットノイズ?皆無にできる
効果があり、CCDの高S/Hに大きな効果がある。
As explained above, the invention is possible by setting the shape, junction depth, and drain voltage of the floating diffusion layer so that it can be completely depleted, even if there is thermal noise in the reset transistor. Reset noise? It has the effect of completely eliminating it, and has a great effect on the high S/H of CCD.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図(a)
 、 (blはその動作を説明するポテンシャル図、第
3図は従来の信号電荷検出回路部分の断面図であり、第
4図(al 、 (b)はその動作を説明するためのボ
テンンヤル図である。 1・・・・・・浮遊拡散層、2・・・・・・MOSトラ
ンジスタ、3・・・・・・リセットトランジスタ、4・
・・・・・リセットドレイン、5・・・・・・出力ゲー
ト、6・・・・・・転送ゲート、7・・・・・・負荷抵
抗、8・・・・・・N−ウェル、 9・・・・・・P+
インカプラ層、10・・・・・・基板。 童 2 図
Figure 1 is a sectional view showing one embodiment of the present invention, Figure 2 (a)
, (bl is a potential diagram to explain its operation, FIG. 3 is a cross-sectional view of a conventional signal charge detection circuit part, and FIG. 4 (al, (b) is a bottom diagram to explain its operation. 1...Floating diffusion layer, 2...MOS transistor, 3...Reset transistor, 4...
...Reset drain, 5...Output gate, 6...Transfer gate, 7...Load resistance, 8...N-well, 9 ...P+
In-coupler layer, 10... substrate. Child 2 figure

Claims (1)

【特許請求の範囲】[Claims] 浮遊拡散層と、その拡散層内の信号電荷をすい出すリセ
ットトランジスタと、前記浮遊拡散層の電位変化を検出
するソース・フォロワー回路とを含む電荷転送装置の信
号電荷検出回路において、前記浮遊拡散層の不純物濃度
は前記リセットトランジスタが導通時に完全に空乏化す
るような値に設定されていることを特徴とする電荷転送
装置の信号電荷検出回路。
In a signal charge detection circuit of a charge transfer device including a floating diffusion layer, a reset transistor for extracting signal charges in the diffusion layer, and a source follower circuit for detecting potential changes in the floating diffusion layer, the floating diffusion layer A signal charge detection circuit for a charge transfer device, wherein an impurity concentration of is set to a value such that the reset transistor is completely depleted when turned on.
JP18641586A 1986-08-07 1986-08-07 Signal-charge detecting circuit of charge transfer device Pending JPS6342170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18641586A JPS6342170A (en) 1986-08-07 1986-08-07 Signal-charge detecting circuit of charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18641586A JPS6342170A (en) 1986-08-07 1986-08-07 Signal-charge detecting circuit of charge transfer device

Publications (1)

Publication Number Publication Date
JPS6342170A true JPS6342170A (en) 1988-02-23

Family

ID=16188020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18641586A Pending JPS6342170A (en) 1986-08-07 1986-08-07 Signal-charge detecting circuit of charge transfer device

Country Status (1)

Country Link
JP (1) JPS6342170A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423334A (en) * 1990-05-14 1992-01-27 Nec Corp Charge transfer device
US5221852A (en) * 1991-02-01 1993-06-22 Fujitsu Limited Charge coupled device and method of producing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62113473A (en) * 1985-11-13 1987-05-25 Matsushita Electronics Corp Charge transfer device and drive method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62113473A (en) * 1985-11-13 1987-05-25 Matsushita Electronics Corp Charge transfer device and drive method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423334A (en) * 1990-05-14 1992-01-27 Nec Corp Charge transfer device
US5221852A (en) * 1991-02-01 1993-06-22 Fujitsu Limited Charge coupled device and method of producing the same

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