JPS6346992B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing an insulated gate field effect transistor having an offset gate structure.
In this specification, the offset gate is used for simplicity.
OG (offset gate), insulated gate field effect transistor is called IGFET, (Insulated Gate Field Effect
Transistor), IGFET with offset gate structure
It is called OG-IGFET. Regular IGFETs without OG have superior characteristics compared to bipolar transistors, such as smaller element size, higher input impedance, and simpler manufacturing methods, so they are suitable for various integrated circuits such as digital or analog. Widely applied. In order to increase the degree of integration and realize large-scale integrated circuits, further miniaturized IGFETs,
It is necessary to use a so-called HMOS.

However, the breakdown voltage between the drain and source of the HMOS-IGFET, ie, the breakdown voltage, is around 10V at most. IGFETs can also be applied to high voltage elements such as drive circuits for display devices and high voltage switching circuits, but with conventional structures, the voltage resistance is around several tens of volts at most. Therefore, miniaturized IGFETs for these large-scale integrated circuits and display devices
In recent years, there has been a particular demand for higher voltage resistance of IGFETs. As is well known, DSA (Diffusion Self
-alignment) structure or the OG-IGFET shown in Figure 1 have been developed, and the withstand voltage of the device has improved dramatically.

In FIG. 1, 1 is a semiconductor substrate with a low impurity concentration, and 2 and 3 are a drain region and a source region, respectively, which have a conductivity type different from that of the semiconductor substrate 1 and have a high impurity concentration.

4 is a gate insulating film, 5 is a gate, and by changing the gate voltage, a channel region 6 directly below the gate and near the boundary between the gate insulating film and the semiconductor substrate forms an inversion layer, and the electric current is Conduction is controlled. A semiconductor layer, that is, an OG region 7, is in contact with the channel region and the drain region, respectively.
is formed. The OG region is a semiconductor layer having the same conductivity type as the drain region and the source region, but having a different impurity concentration (usually a low concentration);
Its length in the channel direction is indicated by 8. 9 and 10 are electrodes of the drain and gate regions, respectively. A gate voltage of an appropriate magnitude is applied between the gate 5 and the source electrode 10 to form an inversion layer in the channel region 6. When the potential difference between the drain electrode 9 and the source electrode 10, that is, the drain voltage is small, the charge carriers injected from the source region 3 into the channel region 6 further flow into the OG region 7 and into the drain region 2. Flow into. in this case
OG region 7 performs exactly the same function as drain region 2.

When the drain voltage increases, the semiconductor substrate 1 and
A depletion layer expanding from the junction with the OG region 7 causes pinch-off within the OG region 7. Therefore, a large voltage drop occurs in the OG region 7 in the direction of the drain region 2 and source region 3, and the effective voltage applied to the channel region 6 decreases, making it possible to limit it to below the breakdown voltage of the channel region. For this reason, the channel region 6 is not destroyed and high voltage resistance can be achieved.

The OG-IGFET with such a configuration appears to be
A semiconductor substrate 1 serves as a gate electrode, and is formed in a junction field effect transistor and a channel region 6 that control electrical conduction in an OG region 7.
It can be regarded as equivalent to a circuit in which IGFETs are connected in series, that is, the circuit shown in FIG.

In FIG. 2, 11 and 12 are the junction field effect transistor and the junction field effect transistor, respectively.
In the IGFET, M indicates the connection point between both transistors. Therefore, as the drain voltage increases,
The junction field effect transistor 11 causes a pinch-off, and the voltage applied to the IGFET 12, that is, the voltage between the M point and the S (source) terminal, increases as the drain voltage, that is, the voltage at the D (drain) terminal, increases. It remains almost constant. If the pinch-off voltage of the junction field effect transistor 11 is appropriately selected,
The voltage applied to the IGFET 12 can be selected to be below the breakdown voltage of the IGFET 12. This is because the junction field effect transistor 11 absorbs the increase in drain voltage, and it becomes possible to increase the breakdown voltage of the OG-IGFET.

The current flowing through the OG region 7 (Fig. 1), that is, the junction field effect transistor 11 (Fig. 2), is
Regardless of whether or not OG region 7 is experiencing pinch-off, it is proportional to the amount of impurities in OG region 7, and OG
It is inversely proportional to the length 8 of the region in the channel direction. Therefore, in addition to achieving high breakdown voltage and low on-resistance of the OG-IGFET, in order to always achieve the desired device characteristics without variation, the amount of impurities in the OG region 7 and the length 8 in the channel direction must be adjusted. It is important to keep it constant regardless of the manufacturing process.

Using FIGS. 1 and 2 above, the channel area 6
An OG-IGFET including the OG region 7 only between the drain region 2 and the drain region 2 has been described. On both sides of gate 5,
That is, FIG. 3 shows an equivalent circuit of an OG-IGFET having OG regions between the gate 5 and the drain region 2 and between the gate 5 and the source region 3, respectively. In the figure, 13 is an apparent junction field effect transistor formed in the OG region between the drain region and the channel region, 14 is the IGFET formed in the channel region, and 15 is the OG region between the channel region and the source region. This is an apparent junction field effect transistor formed. The OG-IGFET
Since it is bidirectional, its operation and function are essentially the same as those of the OG-IGFET shown in FIG. 1 or FIG. 2, so the explanation thereof will be omitted here.

The conventional manufacturing process of the OG-IGFET shown in FIG. 3 will be explained with reference to FIGS. 4a to 4e, which are cross-sectional views of the semiconductor substrate in the channel direction. As shown in FIG. 4a, a relatively low concentration semiconductor substrate 21 is prepared, and an insulating film 22 is formed on the surface of the semiconductor substrate 21. Next, as shown in FIG. 4b, the portions of the insulating film 22 where the drain region, OG region, channel region, and source region will be formed are removed by photolithography, and then an insulating film is added to the exposed surface of the semiconductor substrate 21. form 23. Next, a metal film 240 such as a polysilicon layer with a high impurity concentration is formed on the insulating film 23. Next, the metal film 240 is removed by photolithography, leaving the portions that will become the gates and gate bus lines, resulting in a structure as shown in FIG. 4C. 24 is the gate, and the gate bus line is not shown. Next, impurities of a conductivity type different from that of the semiconductor substrate 21 are introduced into the semiconductor substrate 21 by diffusion or ion implantation, and the semiconductor layer 250 is
to form. A portion of the semiconductor layer 250 becomes OG regions 251 and 252, which will be described later. At this time,
The gate 24 and the thick insulating film 22 serve as a selective mask for the impurity. Next, a thick insulating film 26 is formed on the surface of the semiconductor substrate 21 including the gate 24, and then, using photolithography, a portion where a drain region and a gate region will be formed is etched as shown in FIG. 4d. The thick insulating film is removed. Next, a high concentration impurity layer of a conductivity type different from that of the semiconductor substrate 21 is formed in the semiconductor substrate 21 to serve as a drain region 27 and a source region 28 . Note that the impurity concentration of the drain and source regions is usually much higher than that of the OG regions 251 and 252. Then, after removing the insulating film 26, the semiconductor substrate 2
A thick insulating film 29 is formed on the surface of the drain region 27, as shown in FIG. 4e, and the drain region 27,
Gate extraction part (not shown), source region 2
Expose 8. Next, a metal film for wiring is deposited, and a drain electrode, a gate electrode (not shown), and a source electrode 32 are formed again using photolithography.
Next, although not shown, a protective insulating film is further formed, and then the metal portion of the bonding pad to which the drain electrode, gate electrode, and source electrode are connected is exposed.

The typical manufacturing process for conventional high-voltage OG-IGFETs has been described above. It is desirable to eliminate variations in device characteristics between wafers or between lots that occur during the device manufacturing process. For this purpose, it is necessary to always keep the impurity content and length in the channel direction of the OG region 7 shown in FIG. 1 or the OG regions 251 and 252 shown in FIG. 4 constant. The problem of variations in the amount of impurities can be solved relatively easily by using ion implantation technology. However, as is clear from the process shown in Figure 4d, in the conventional manufacturing method, the OG region 2
The lengths of 51 and 525 in the channel direction are the lengths of gate 24 and drain region 27 or source region 2.
8 is determined by two steps for forming. Therefore, since errors due to mask alignment occur for each wafer, the lengths of the OG regions 251 and 252 in the channel direction are set to different values for each wafer. As a result, even under the same driving conditions, the drain current, breakdown voltage, and other characteristics of the OG-IGFET manufactured using the conventional manufacturing method vary from wafer to wafer, which is a serious disadvantage of device-to-device variation. A shortcoming occurred.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to provide a high-voltage OG-3 that is independent of manufacturing conditions and that has consistent device characteristics between wafers and lots.
This provides a manufacturing method for realizing an IGFET.

According to the present invention, a low concentration impurity semiconductor of the same conductivity type as the drain region is formed in the semiconductor substrate between the drain region and the channel region directly under the gate, and between the channel region and the source region. In an insulated gate field effect transistor having an offset gate region, metal films identical to the gate, that is, a first metal film and a second metal film, are formed on both sides of the gate at the same time as the gate; Next, after covering the gap between the gate and the first metal film and the gap between the gate and the second metal film with a mask material such as an insulating film or a metal layer different from the gate, the drain region and the second metal film are covered. After forming a source region and then removing the mask material and the first and second metal films in sequence, forming the offset region and adjusting the length of the offset gate region in the channel direction with respect to the gate. There is obtained a method for manufacturing an insulated gate field effect transistor, characterized in that the method is determined by self-alignment.

Further, according to the present invention, an insulated gate field effect transistor is provided with an offset gate region made of a low concentration impurity semiconductor having the same conductivity type as the drain region in the semiconductor substrate between the drain region and the channel region directly under the gate. , a metal film identical to the gate is formed on the drain side of the gate at the same time as the gate, and then the gap between the gate and the metal film is covered with a mask material such as an insulating film or a metal layer different from the gate. After that, the drain region and the source region are formed, and then the mask material and the metal film are sequentially removed, and then the offset region is formed, and the offset region is formed in the channel direction of the offset gate region with respect to the gate. A method for manufacturing an insulated gate field effect transistor characterized in that the length is determined by self-alignment is obtained.

An embodiment of the method for manufacturing a high voltage OG-IGFET according to the present invention will be described below with reference to FIGS. 5a to 5f.

In this embodiment, as an example, there is an OG on both sides of the gate.
This will be explained using an OG-IGFET (see Fig. 3) having a region.

First, as shown in FIG. 5a, a semiconductor substrate 41 having a relatively low impurity concentration, for example, 1×10 ¹⁵ /cm ³ is prepared, and an insulating film 42 is formed on the surface of the semiconductor substrate 41. As shown in FIG. Next, as shown in Figure 5b, the drain region, OG
After removing the insulating film 42 in the portions where the region, channel region, and source region will be formed by photolithography, a new thickness is applied to the exposed surface of the semiconductor substrate 41.
An insulating film 43 such as a silicon oxide film having a thickness of 400 angstroms to 1000 angstroms is formed. Thereafter, a metal film 44 made of polysilicon or the like with a high impurity concentration is formed on the edge film 43 to a thickness of approximately 5000 angstroms.

Next, as shown in FIG. 5c, the gate 45, the first metal film 451, the second metal layer 452, and a portion that will be a gate bus line (not shown) are left.
Using photo-etching technology, the metal film 4 shown in FIG. 5b is
Remove 4.

Next, the gate 45, the first metal film 451, the second
An insulating film used as an impurity selective diffusion mask is formed on the surface of the semiconductor substrate 41 including the metal film 452, and then the insulating film, the gap between the gate 45 and the first metal film 451, and the gate 45 and the second
The excess portion is removed by photolithography so as to cover the gap with the metal film 452, ie, as shown in 46 in FIG. 5c. In other words, the insulating film 46 starts on the first metal film 451 , covers the two gaps and the gate 45 , and ends on the second metal film 452 .
At the same time, after exposing the surface of the semiconductor substrate 41 that will become the drain region and the source region, a conductivity type different from that of the semiconductor substrate 41 and a high concentration, for example, 5×10 ¹⁵ /
An impurity layer of cm ³ , ie, a drain region 47 and a source region 48, is formed. Here, the drain region 47 and the source region 48 are self-aligned with the first metal film 451 and the second metal film 452, respectively.

Note that the insulating film 46 is an insulating film such as a silicon oxide film or a nitride film, or a metal film 45, 451, 452.
Any material may be used as long as it has a desired masking effect, such as another polysilicon film formed thereon with an insulating film interposed therebetween. The drain region 47 and the source region 4
Any method, such as diffusion or ion implantation, may be used to form 8. Next, the insulating film 46 is partially removed using photolithography.

That is, the insulating film 46 is removed so that the gate 45 is completely covered with the insulating film and the first metal film 451 and the second metal film 452 are exposed. The result is shown in FIG. 5d. The gate 45
is completely included in the insulating film (here, it is referred to as 49). Next, after removing the exposed first metal film 451 and second metal film 452, the insulating film 43 immediately below the first and second metal films 451 and 452 is also removed to expose the semiconductor substrate 41.

Note that the gap between the gate 45 and the first metal film 451 or the gap between the gate 45 and the second metal film 45
If the gap distance with 2 is extremely short and it is difficult for the insulating film 49 to start at one gap and end at the other gap as shown in FIG.
492, the insulating film 491 shown by the dotted line is terminated at a position extremely close to the left end of the first metal film 451 and a position extremely close to the right end of the second metal film 452. and 492
Both metal films directly below may be removed by overetching.

Next, the semiconductor substrate 4 is placed on the exposed semiconductor substrate 41.
Impurities of a conductivity type different from 1 are introduced by ion implantation or the like to form semiconductor layers 50 and 51 of low concentration impurities, as shown in FIG. 5e. Note that the ion implantation may be performed after forming an insulating film such as a thin silicon oxide film on the surface of the semiconductor substrate 41. When the semiconductors 50 and 51 are formed, since the gate 45 and the thick insulating film 42 act as a selective mask for the impurities, the semiconductor substrate 41 directly under the gate 45, that is, the channel region and the drain region 4,
7 and between the channel region and the source region 47, a first OG region 50 and a second OG region 51 each having a low impurity concentration are connected to each other.
is formed. At this time, the first OG region 50 is self-aligned with the gate 45 and the drain region 47, and as described above, the drain region 47 is also aligned with the gate 45 and the drain region 47.
5, the length of the first OG region 50 in the channel direction is self-aligned with the gate 45. For similar reasons, the second
The length of the OG area 51 in the channel direction is determined by gate 4.
Self-aligned to 5. Next, the semiconductor substrate 41
A thick insulating film 52 is formed on the surface of the insulating film 52 as shown in FIG. expose. Next, a metal film for wiring is deposited, and a drain electrode 53, a gate electrode (not shown), and a source electrode 54 are formed again by photolithography. Next, although not shown, after further forming an insulating film, a drain electrode,
Expose the metal part of the bonding pad to which the gate electrode and source electrode are connected.

In the above explanation, the OG area is one on each side of the gate.
Although we have explained the manufacturing method for OG-IGFETs with a structure in which individual gates are provided, the same manufacturing method can also be applied to OG-IGFETs that are formed only on one side of the gate, as in the structure shown in Figure 1. That is clear.

According to the present invention, first and second metal films are formed on both sides of the gate at the same time as the gate, and the gap between the gate and the first metal film and the gap between the gate and the second metal film are masked. If a drain region and a source region are formed in the semiconductor substrate with an impurity of a conductivity type different from that of the semiconductor substrate after being covered with a material such as an insulating film or another metal layer, the drain region and the source region can be formed as a gate. , that is, self-aligned with the channel region. Next, only the gate is left and the first and second metal films are removed, and then between the channel region and the drain region and between the channel region and the source region formed in the semiconductor substrate directly under the gate, respectively. When the first OG region and the second OG region are formed, one end of the first and second OG region is self-aligned with the gate, and the other end is formed by self-alignment with the gate. are self-aligned with the drain region or source region, respectively.
Therefore, the lengths of the first and second OG regions in the channel direction are self-aligned with respect to the gate. Similarly, in the case of an OG-IGFET having an OG region only on one side of the gate as shown in FIG. 1, the length of the OG region in the channel direction is self-aligned with the gate. As is clear from the above, by using the manufacturing method of the present invention, the length of the OG region in the channel direction can always be made equal to the desired design value, so there is no variation between devices. It is possible to realize devices with excellent characteristics and high yields.

Furthermore, according to the present invention, the length of the OG region is set by the distance between the edge of the gate and the edge of the metal film on the opposite side of the gate, so the length of the OG region can be freely selected.
Can be designed. Furthermore, the gap distance between the gate and the metal film and the width of the metal film (the sum of the two is the length of the OG region) can be dramatically reduced as processing technology improves, allowing for high voltage and high power consumption. for OG−
It is extremely advantageous not only as an IGFET but also as a fine element for large-scale integrated circuits.

Furthermore, according to the present invention, the length of the OG region is always constant from wafer to wafer, and other factors that determine device characteristics, that is, the impurity concentration of the OG region, can be determined extremely accurately by ion implantation, etc. , there is no need to give much consideration to margins for variations in device characteristics when designing devices.
Therefore, the switching speed, frequency characteristics, offset voltage, distortion characteristics, etc. of the device can be equal to or extremely close to the designed values. Similarly, even if there is an OG region on only one side of the gate, the length of the OG region in the channel direction is self-aligned with the gate, so the OG-IGFET with OG regions on both sides of the gate is It is clear that they exhibit exactly the same characteristics.

Note that the insulating film thickness used in the examples described above,
The metal film thickness, impurity concentration, etc. are just examples, and are not limited to these values, and any values can be freely selected as appropriate. The materials used for the insulating film, metal film, etc. are merely examples, and any material may be used as long as the function of the present invention is achieved. Furthermore, any method of forming an insulating film, a metal film, or an impurity semiconductor layer such as a drain, source, or OG region can be adopted as long as the above object is achieved.

In the above embodiments, an insulating film is used to cover the gap between the gate and the first metal film or between the gate and the second metal film, but impurities forming the drain and source regions are added to the semiconductor substrate directly under the gap. If it is not introduced, that is, if it exhibits a masking effect, any material can be used not only for the insulating film but also for the metal film.

Photographic etching techniques are not limited to dry etching or wet etching, provided the desired purpose is achieved.

[Brief explanation of drawings]

Figure 1 is a schematic diagram showing the structure of an insulated gate field effect transistor (IGFET) with a high withstand voltage offset gate (OG) structure. is the equivalent circuit of the OG-IGFET shown in FIG.
Figure 3 shows an OG type with OG areas on both sides of the gate.
This is an equivalent circuit of IGFET. Figure 4 a to 4
FIG. e is a diagram for explaining a conventional manufacturing method for forming the OG-IGFET shown in FIG. 3.
FIGS. 5a to 5f are diagrams for explaining one embodiment of the present invention, and are diagrams for explaining the manufacturing process for forming an OG-IGFET. In the figure, 1 is a semiconductor substrate, 2 is a drain region, 3 is a source region, 4 is a gate insulating film, 5 is a gate, 6 is a channel region, 7 is an offset region,
8 is the length of the offset gate region in the channel direction, 9 and 10 are a drain electrode and a gate electrode, respectively, 11, 13, and 15 are junction field effect transistors, 12 and 14 are insulated gate field effect transistors, and 21 are insulated gate field effect transistors. semiconductor substrate, 22,2
3, 26, 29 are insulating films, 240, 24 are metal films, 251, 252 are offset gate regions,
27 is a drain region, 28 is a source region, 31 is a drain electrode, 32 is a source electrode, 41 is a semiconductor substrate, 42, 43, 46, 49, 52 are insulating films,
44, 45, 451, 452 are metal films, especially 45
47 is a drain electrode, 48 is a source region, 50 and 51 are offset gate regions, 53 is a drain electrode, and 54 is a source electrode.

Claims (1)

[Claims] 1. In the semiconductor substrate between the drain region and the channel region directly under the gate, and between the channel region and the source region, from a low concentration impurity semiconductor of the same conductivity type as the drain region, respectively. offset. In an insulated gate field effect transistor having a gate region, metal films identical to the gate, that is, a first metal film and a second metal film, are formed on both sides of the gate at the same time as the gate;
Next, after covering the gap between the gate and the first metal film and the gap between the gate and the second metal film with a mask material such as an insulating film or a metal layer different from the gate, the drain region and the source region are covered. form,
Next, after sequentially removing the mask material and the first and second metal films, the offset region is formed, and the length of the offset region in the channel direction with respect to the gate is determined by self-alignment. A method of manufacturing an insulated gate field effect transistor, characterized in that: 2. In an insulated gate field effect transistor comprising an offset gate region made of a low concentration impurity semiconductor of the same conductivity type as the drain region in a semiconductor substrate between the drain region and a channel region directly under the gate, the drain region of the gate A metal film identical to that of the gate is formed on the side at the same time as the gate, and then, after covering the gap between the gate and the metal film with a mask material such as an insulating film or a metal layer different from the gate, the drain region is and form a source region,
Next, after sequentially removing the mask material and the metal film, the offset region is formed, and the length of the offset region in the channel direction with respect to the gate is determined by self-alignment. A method for manufacturing an insulated gate field effect transistor.