JPS6347979A - Thin film transistor - Google Patents

Abstract

PURPOSE:To reduce the OFF current of a thin film transistor which uses a CdSe polycrystal without considerably complicating an element structure and to decrease the irregularity of each OFF current element by covering the surface of a CdSe polycrystalline thin film opposite to a gate insulating film with a P-type semiconductor. CONSTITUTION:A gate electrode 2 is disposed through a gate insulating film 3 on one side surface of a CdSe polycrystalline thin film 4, source and drain electrodes 5, 6 are disposed at predetermined parts of the film 4, and the other side surface 8 of the film 4 is covered with a P-type semiconductor 19. For example, aluminum is deposited on a glass substrate 1 to form the gate electrode 2, alumina is deposited thereon by a sputtering method to form the film 3. Then, the film 4 is deposited, an unnecessary part is removed by a lifting off method, aluminum is then deposited to form the electrodes 5, 6. Further, after a resist pattern is formed on the upper surface, the P-type CdTe polycrystalline thin film 19 is deposited, and the unnecessary part is removed by a lifting off method.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film transistor that constitutes a field effect transistor mainly consisting of a cadmium selenide (CdSe) polycrystalline thin film formed on an insulating substrate.

Prior Art A typical conventional structure of a thin film transistor using CdSe polycrystal is shown in FIG.

In FIG. 3, 1 is a glass substrate, 2 is a gate electrode, and 3 is a glass substrate.
4 is a gate insulating film, 4 is a CdSe polycrystalline thin film, 5 is a source electrode, and 6 is a drain electrode, which constitute a field-effect thin film transistor. Note that 7 indicates the interface between the gate insulating film 3 and the CdSe polycrystalline thin film 4, and 8
is the CdSe polycrystalline thin film 4 on the opposite side of this interface 7.
Refers to the surface (top side of the figure). In the following description, this front surface 8 will be referred to as the back surface 8 of the CdSe polycrystalline thin film 4.

In the above configuration, the source electrode 5, the drain electrode 6,
When the potential of the gate electrode 2 is set to 0 volts, +10 volts, and +10 volts, an electron storage layer is induced on the interface 7 side of the CdSe polycrystalline thin film 4, and this becomes a channel for current between the source and drain, and the thin film transistor is turned on.
state.

The OFF state is realized by setting the potentials of the source electrode 5, drain voltage 56, and gate electrode 2 to O volts, +10 volts, and 0 volts, respectively.

FIG. 4 is a band diagram near the drain in the OFF state.

In FIG. 4, numerals 2, 3, and 4 are the aforementioned gate electrode, gate insulating film, and Cd Se polycrystalline thin film, respectively. Further, 9 is the Fermi level of the gate electrode metal, 10 is the bottom end of the conduction band of the gate insulating film 3, 11 is the bottom end of the CdSe conduction band, 12 is the top end of the CdSe full band, and 13 is the Fermi level of CdSe. are shown respectively.

In the vicinity of the source electrode 5, the potential of the gate electrode 2 and the CdS
e The potentials of the polycrystalline thin film 4 are approximately equal. However, in the vicinity of the drain electrode 6, the potential of the gate electrode 2 is lower than the potential of the CdSe polycrystalline thin film 4.

Therefore, an electron depletion layer 14 is generated on the interface 7 side of the CdSe polycrystalline thin film 4 near the drain. This electron depletion layer 1=
4 does not become a current path. The current path in the OFF state is the flat band portion 16 of the CdSe polycrystalline thin film 4 and the bent band portion 15 on the back surface 8 side.

Problems to be Solved by the Invention In the conventional thin film transistor having the structure shown in FIG.
There is a problem in that the FF current (current flowing in the OFF state) is relatively large, and the OFF current varies widely from element to element.

As explained in FIG. 4, the path of the OFF current is between the band flat part 16 and the band bent part 15 on the back side 8, and especially when the band bent part 15 is bent downward as shown in the figure, Since an electron storage layer is generated in the area and becomes a current path, O
The FF current becomes considerably large.

Whether the band bending portion on the back surface 8 side of the CdSe polycrystalline thin film 4 is bent upward or downward is determined by the surface condition of the back surface 8. In the conventional technology, since the surface condition of the back surface 8 is not controlled, the OFF current varies from element to element, and the O
It has been difficult to uniformly manufacture thin film transistors with small FF currents.

As a technique for solving the above problem, a double gate structure shown in FIG. 5 has been proposed.

As shown in FIG. 5, a gate insulating film 17 is also formed on the back side of the CdSe polycrystalline thin film 4, and a gate electrode 18 is formed thereon. The gate electrode 18 is at the same potential as the gate electrode 2. In this double gate structure, in the OFF state, the same depletion layer as that on the interface side is generated on the back surface side of the Cd Se polycrystalline thin film 4, so that the OFF current can be kept small.

Although the above-mentioned problems can be solved by using a double gate structure as described above, there is another problem in that the additional structure for this purpose becomes very complicated.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to
The object of the present invention is to reduce the OFF current of a thin film transistor using CdSe polycrystal and to reduce the variation in OFF current from element to element.

Means to Solve the Problems Therefore, in the present invention, a structure is adopted in which the surface of the Cd Se polycrystalline thin film opposite to the gate insulating film (the back surface) is covered with a P-type semiconductor.

Effect When the CdSe polycrystalline thin film and the P-type semiconductor come into contact with each other, the band bends upward, and an electron depletion layer is formed on the side of the CdSe polycrystalline thin film near the interface between the two. Therefore, this portion does not become a path for the OFF current.

Further, by bringing a P-type semiconductor into contact with the CdSe polycrystalline thin film, this portion always exhibits a certain band bending, so that the device characteristics become uniform.

Embodiment FIG. 1 shows the structure of a thin film transistor according to an embodiment of the present invention. This will be explained below according to the manufacturing process.

Aluminum is first deposited on a glass substrate 1, and a gate electrode 2 is formed by lithography.

Next, a gate insulating film 3 is formed by depositing alumina thereon by sputtering. Then add Cd
A Se polycrystalline thin film 4 having a thickness of 300λ is deposited, and unnecessary portions are removed by a lift-off method. Next, aluminum is vapor-deposited thereon, and a source electrode 5 and a drain electrode 6 are formed by a lift-off method. Up to this point, the manufacturing process is the same as the conventional one (FIG. 3).

In the present invention, after forming a regimen pattern on the upper surface of the element to remove unnecessary portions by a lift-off method, sintered cadmium chillide (CdTe) powder containing 250 ppm of copper is used as an evaporation source to deposit P. Type CdTe
A polycrystalline thin film 19 is deposited for 1000 times, and the important portions of the film are removed by a lift-off method. As a result, an element structure is completed in which the surface 8 of the CdSe polycrystalline thin film 4 opposite to the gate insulating film 3 is covered with a P-type CdTe polycrystalline thin film 19.

In a thin film transistor having this structure, when the potential of the source electrode 5 and the gate electrode 2 is set to O volts, and the potential of the drain electrode 6 is set to +10 volts, it becomes an OFF state.
FIG. 2 is a band diagram near the drain in this state.

(By coating the surface 8 of the 'dSe polycrystalline thin film 4 on the side opposite to the gate insulating film 3 with the P-type CdTe polycrystalline thin film 19, an electron depletion layer is generated on the CdSe side of the interface between the two, and this part Therefore, the OFF current becomes small.Since the band bending state on the surface 8 side can be controlled to be constant, the uniformity of device characteristics can be improved.

In the above embodiment, P-type CdTe polycrystal was used as the P-type semiconductor covering the surface 8 of the CdSe polycrystalline thin film 4, but other materials such as P-type amorphous silicon may be used as the P-type semiconductor. The same effects can be obtained. P-type amorphous silicon can be deposited by a plasma CVD method using silane gas containing diborane at a substrate temperature of 300C or less. Effects of the Invention As explained in detail above, according to the present invention, Cd
By simply covering the surface of the Se polycrystalline thin film opposite to the gate insulating film with a P-type semiconductor, it is possible to reduce the OFF current of this type of thin film transistor and to improve the uniformity of device characteristics. can be increased.

[Brief explanation of drawings]

FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a band diagram of the thin film transistor shown in FIG. 1 in an OFF state, FIG. 3 is a schematic structural diagram of a typical conventional thin film transistor, and FIG. The figure is a band diagram of the one shown in FIG. 3 in an OFF state, and FIG. 5 is a schematic structural diagram of a conventional double-gate thin film transistor. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Gate electrode, 3... Gate insulating film, 4... CdSe polycrystalline thin film, 5... Source electrode, 6... Drain electrode, 19... P Type Cd
Name of Te polycrystalline thin film agent: Patent attorney Toshio Nakao and 1 other person 1m t2! ! 1? 3 4
, Guq:″H

Claims (3)

[Claims] (1) A gate electrode is arranged on one surface of the CdSe thin film via a gate insulating film, and a source electrode and a drain electrode are arranged in a predetermined part of the CdSe polycrystalline thin film, and the other surface of the CdSe polycrystalline thin film is arranged. A thin film transistor coated with a P-type semiconductor. (2) The thin film transistor according to claim 1, which uses P-type CdTe polycrystal as the P-type semiconductor. (3) The thin film transistor according to claim 1, in which P-type amorphous silicon is used as the P-type semiconductor.