JPS6353573B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing system having a storage device consisting of a ROM and a RAM, and a microprogram type processing device, in which an area of the RAM that overlaps with the ROM is set as a collection of registers separate from the memory space. This relates to a data processing system that can be used as a computer.

Storage devices have traditionally been composed of ROM and RAM, but conventional ROM and
Figure 1 A shows the address assignment for RAM.
Something like Ro is known. In FIG. 1, 1 indicates ROM and 2 indicates RAM. In Figure 1 A and B, addresses 0 to N are allocated to ROM1, and addresses N+ to RAM2 are allocated.
The 1st address to the Mth address are allocated. Now, assuming that ROM1 is 2K bytes and RAM2 is 64K bytes, addresses 0 to 2057 are allocated to ROM1, and addresses 2058 to 2058 are allocated to RAM2.
Address 67593 will be allocated. In addition, 1 word is 8
It is said that it is a bit. However, if the width of the address bus from the processing unit is 16 bits, the 0th
It is only possible to access addresses up to the 65535th address, resulting in an address area in RAM2 that cannot be accessed.

The present invention is based on the above considerations, and includes:
To provide a data processing system having a storage device consisting of ROM and RAM and a microprogram type processing device, which can use the entire address area of RAM even when the width of an address bus is not wide enough. The purpose is to And to that end, the data processing system of the present invention comprises: local storage 4, arithmetic logic unit 5, interrupt flag register 6, data register 7, address register 8, program counter 9, microprogram counter 10 and microinstruction A microprogram type processing device 3 having a register 11, a ROM1, and a storage area having an address that overlaps with ROM1.
RAM2, an address bus for sending the address of address register 8 to ROM1 and RAM2, and data for transferring data between data register 7 and ROM1 and between data register 7 and RAM2.・ROM that controls access to the bus and ROM1
It is equipped with selection signal generation means 12, 13, 14, 15, 16, and 17 that generates a selection signal and a RAM selection signal that controls whether or not RAM 2 can be accessed. A table used to find the start address of a microroutine corresponding to a machine instruction or an interrupt handling routine, a stack that stores the return address from a subroutine, and various registers are allocated to the system, and a selection signal Generation means 12, 13, 14, 15, 1
6 and 17 indicate that a memory request has been issued from the processing device 3, that the address on the address bus exists within a predetermined range, and that the microinstruction register 11
On the condition that a predetermined type of microinstruction does not exist in the ROM selection signal, the ROM selection signal is set to a value that allows access, and when a memory request is issued from the processing unit 3 and the address on the address bus does not exist within the predetermined range, is characterized in that it is configured to set the RAM selection signal to a value that allows access, and also to set the RAM selection signal to a value that allows access even when a predetermined type of microinstruction exists in the microinstruction register 11. It is something to do. Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing an example of address allocation in the present invention, FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a diagram showing an example of the structure of the overlapping address area of RAM, and FIG. This figure is a diagram for explaining a subroutine stack, and FIG. 6 is a diagram for explaining I/O interrupt control.

As shown in FIG. 2, in the present invention, the ROM
Addresses 0 to N are assigned to RAM 2, and addresses 0 to MN are assigned to RAM 2. The shaded area of RAM2 indicates an overlapping address area. ROM1 and RAM2
microprograms, control programs, processing programs, and data are stored in the .

FIG. 3 is a block diagram of one embodiment of the present invention, in which 3 is a microprogram type processing device, 4 is a block diagram of an embodiment of the present invention;
is local storage, 5 is an arithmetic logic unit, 6 is an interrupt flag register, 7 is a data register, 8
is an address register, 9 is a program counter, 10 is a microprogram counter, 11
is a microinstruction register, 12 is a decoder, 13
and 14 are NOT circuits, 15 and 16 are AND circuits, 1
7 indicates an OR circuit.

Now, address 0 to 2047 for ROM1
addresses are allocated, addresses 0 to 65535 are allocated to RAM2, and addresses
Assume the bus width is 16 bits. Assuming that the address information is A0 bits to A15 bits,
The decoder 12 outputs a RAM designation signal of logic "1" when each of A11 to A15 is logic "0", and outputs a logic "0" RAM designation signal in other cases.
Outputs ROM specification signal. For example, the register designation signal becomes logic "1" when the microinstruction set in the microinstruction register 11 is a branch function instruction or a push instruction. Therefore, the chip supplied to ROM1
The select signal becomes logic "1" when all bits A11 to A15 are logic "0", the register designation signal is logic "0", and the memory request signal is logic "1". The chip select signal supplied to RAM2 becomes logic "1" when the memory request signal is logic "1" and the ROM designation signal is logic "0" or when the register designation signal is logic "1". .

FIG. 4 shows the structure of the address area of RAM2 which overlaps with ROM1. In FIG. 4, BF0 to BF3 are branch tables,
SS indicates a subroutine stack. The branch table is used, for example, to find the start address of a microroutine corresponding to a machine instruction or to find the start address of an interrupt processing microroutine. The subroutine stack SS is for stacking return addresses. FIG. 5 shows an example of the start address, and i+1, j+1, and k+1 each indicate a return address. subroutine·
The stack SS has return addresses i+1, j+1, k.
+1 is stacked.

FIG. 6 explains IO interrupt control, and IO1 to IO3 indicate input/output devices.
The interrupt flag register 6 (see Figure 3) has bits corresponding to each of the input/output devices IO1 to IO3, and when an interrupt is generated from the input/output device, the corresponding flag bit is set. Logic "1"
It is said that The contents of the interrupt flag register 6 are sensed at a predetermined timing, but when the interrupt flag register 6 is "000", address A is read out.
When it is "001", address B is read out, and when it is "010", address C is read out. The following is as shown in the figure.

Next, the present invention will be explained by taking as an example the case of finding the start address of a microroutine corresponding to a machine instruction. Note that the branch used in this case is
Assume the table is BF0. In order to obtain the start address of a microroutine corresponding to a machine instruction, the OP code of the machine instruction is stored in one register in the local memory 4. Then,
A branch function instruction is set in the microinstruction register 11. The register specification part of the branch function instruction specifies the register in which the OP code of the machine instruction is stored. When the branch function instruction is decoded, the OP code is set in address register 8 and memory access is performed. In this case, the register designation signal is set to logic "1",
Branch table BF0 of RAM2, which overlaps with ROM1, is indexed, and data at the address specified by the OP code is read. This read data or the contents of the microprogram counter modified with this data indicates the start address of the microroutine corresponding to the machine instruction. The read data or modified read data is set in microprogram counter 10 and the microroutine corresponding to the machine instruction is executed.

Next, the present invention will be explained using IO interrupt control as an example. Note that it is assumed that the branch table used in this case is BF1. First, the contents of interrupt flag register 6 are set in one register in local storage 4. And brunch
The contents of this register are read by the function instruction, and branch table BF1 is navigated by the contents. Brunch table BF1
The start address of the interrupt processing program when an I/O interrupt occurs and the start address of the processing program when no interrupt occurs are stored in correspondence with each interrupt pattern. The sum of the indexed data or contents of the microprogram counter and the read data is set in the microprogram counter 10 and the control store is accessed.

When jumping to a subroutine, it is necessary to push the return address onto the subroutine stack SS. A microinstruction called a push instruction is set in the microinstruction register 11 to push a return address onto the subroutine stack SS. When the push instruction is executed, the contents of the stack pointer in local memory 4 are set in address register 8, the contents of program counter 9 plus 1 are set in data register 7, and the contents of subroutine stack SS are set. The return address is stacked.

As is clear from the above description, the data processing system of the present invention is configured so that the RAM address area hidden in the ROM can be used as a collection of registers different from the memory space.
The entire address area of RAM can be used without waste.

[Brief explanation of the drawing]

Figure 1 shows conventional address allocation, Figure 2
The figure shows an example of address allocation according to the present invention, Figure 3 is a block diagram of one embodiment of the present invention, Figure 4 is a diagram showing the configuration of the duplicate address area of RAM, and Figure 5 is a subroutine stack. FIG. 6 is a diagram for explaining I/O interrupt control. 1...ROM, 2...RAM, 3...processing device,
4... Local memory, 5... Arithmetic logic unit,
6...Interrupt flag register, 7...Data register, 8...Address register, 9...Program counter, 10...Microprogram counter, 11...Microinstruction register,
12...Decoder, 13 and 14...Negation circuit, 1
5 and 16...AND circuit, 17...OR circuit.

Claims (1)

[Claims] 1. Local memory 4, arithmetic logic unit 5, interrupt flag register 6, data register 7, address register 8, program counter 9,
A microprogram type processing device 3 having a microprogram counter 10 and a microinstruction register 11, a ROM1, and a storage area having an address that overlaps with the ROM1.
RAM2, an address bus for sending the address of address register 8 to ROM1 and RAM2, and data for transferring data between data register 7 and ROM1 and between data register 7 and RAM2.・ROM that controls access to the bus and ROM1
It is equipped with selection signal generation means 12, 13, 14, 15, 16, and 17 that generates a selection signal and a RAM selection signal that controls whether or not RAM 2 can be accessed. A table used to find the start address of a microroutine corresponding to a machine instruction or an interrupt handling routine, a stack that stores the return address from a subroutine, and various registers are allocated to the system, and a selection signal Generation means 12, 13, 14, 15, 1
6 and 17 indicate that a memory request has been issued from the processing device 3, that the address on the address bus exists within a predetermined range, and that the microinstruction register 11
On the condition that a predetermined type of microinstruction does not exist in the ROM selection signal, the ROM selection signal is set to a value that allows access, and when a memory request is issued from the processing unit 3 and the address on the address bus does not exist within the predetermined range, is characterized in that it is configured to set the RAM selection signal to a value that allows access, and also to set the RAM selection signal to a value that allows access even when a predetermined type of microinstruction exists in the microinstruction register 11. data processing system.