JPS635787B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides parallel synchronous operation control in which a plurality of microcomputers are operated in parallel and synchronously by dividing an input clock signal using a built-in frequency dividing circuit to form a divided signal for operation timing control. Regarding the equipment,
A simple circuit allows the operation control timing of each computer to match, the operation start point of each computer to match, and various operation command signals of external devices to be synchronized with the frequency-divided signal after the formation timing matches. This is intended to improve the reliability of control by having each computer incorporate the information into the system.

Conventionally, microcomputers have been integrated into integrated circuits, and improvements have been made in terms of functionality and processing speed. When high reliability is required for devices using computers (hereinafter referred to as computers), important circuit parts are configured with parallel redundant systems such as N out of M (N out of M) to detect failures. and processing needs to be done automatically.

In order to configure the aforementioned parallel redundant system and detect failures early and reliably, it is necessary to provide a plurality of computers in parallel and to synchronize the machine cycles of each computer to perform parallel synchronous operations.

However, for example, computers that use Intel's 8085A processor use multiple built-in frequency divider circuits that divide the input clock signal to form divided signals for operation timing control. In this case, even if the same clock signal is input to each computer, the formation timing of the divided signal of each computer will not match.
The operation control timings of each computer do not match, making it impossible to match the machine cycles of each computer and making it impossible to perform parallel synchronous operations. Furthermore, in order to perform parallel synchronous operations, it is necessary to make the operation start points of each computer coincident.

Furthermore, each computer operates in synchronization with the frequency-divided signal, and various operation command signals such as interrupt commands from external devices are sent to each computer asynchronously with the frequency-divided signal of each computer, so parallel synchronization is possible. In order to perform an operation, it is necessary to input an operation command signal from an external device into each computer in synchronization with the operation timing of each computer.

The present invention has been made with the above points in mind, and includes a plurality of microcomputers that divide the frequency of an input clock signal using a built-in frequency divider circuit to form a frequency-divided signal for controlling operation timing, and a frequency division signal control circuit that matches the formation timing of the frequency division signal of each of the computers based on the formation timing of the frequency division signal of the computer; A reset control circuit that simultaneously resets and disconnects the computers and synchronizes the operation start time of each of the computers; and a reset control circuit that generates various operation command signals for external devices and synchronizes with the frequency-divided signal after the timings coincide with each other. This is a parallel synchronous operation control device characterized by comprising a command signal control circuit that is input into a computer.

Therefore, the divided signals of each computer are formed at the same timing by the divided signal control circuit.
The operation control timings of each computer match, and the reset control circuit simultaneously cuts off the reset of each computer after the operation timings of each computer match, so the operation start points of each computer match and the command In order for the signal control circuit to input the operation command signal of the external device to each computer at the same timing synchronized with the frequency-divided signal, the operation command signal of the external device that is sent out asynchronously to the frequency-divided signal is sent to the computer at the same timing synchronized with the frequency-divided signal. It is possible to have each computer take in the information at the correct timing, to match the machine cycles of each computer, to perform parallel synchronous operations accurately, and to improve control reliability.

Next, the parallel synchronous operation control device of this invention is
An embodiment thereof will be explained with reference to the drawings from FIG. 1 onwards.

In FIG. 1, 1a and 1b are first and second computers consisting of microcomputers,
It has Intel 8085A type processors 2a and 2b, which each have a built-in frequency dividing circuit for the input clock signal, and peripheral circuits 3a and 3b, respectively.Both processors 2a and 2b each have a clock input terminal ia, an inverted clock input terminal and reset input terminal ib, first to third command input terminal ic,
id, ie, and a frequency division output terminal oa, and both peripheral circuits 3a, 3b are provided with first to third command input terminals if, ig, ih, and first to third command output terminals ob, oc and od are provided.

When the 8085A processor inputs a clock signal to the clock input terminal and an inverted clock signal, which is an inverted version of the clock signal, to the inverted clock input terminal, the built-in frequency divider operates to generate a waveform that is the frequency of the clock signal divided by two. A frequency-divided signal is output from the frequency-divided output terminal, and the processor operates in synchronization with the frequency-divided signal. For example, a logic 0 (hereinafter referred to as "0") reset signal for a reset command is output from the reset input terminal. When the reset signal is input, the reset signal is taken in in synchronization with the first falling change of the frequency division signal from logic 1 (hereinafter referred to as "1") to "0" after the input of the reset signal, and the processor initializes. At the same time as the reset, a reset display signal of "1" is output from the reset output terminal (not shown) of the processor in synchronization with the change in the frequency division signal rising from "0" to "1" again.
That is, a signal indicating that it is in a reset state is output.

Furthermore, when the reset signal is briefly cut off and the level of the reset input terminal rises from "0" to "1", the initial change of the divided signal from "1" to "0" after the reset signal is briefly cut off. The ebb and flow of the reset signal is detected in synchronization with the falling change, and the reset display signal of "1" is output from the reset output terminal in synchronization with the change in the divided signal rising from "0" to "1" again. The processor starts operating according to the program.

Further, in FIG. 1, 4 is a clock oscillator that outputs a clock signal to the clock input terminal ia of the processor 2a, and 5 is a first inverter that inverts the clock signal and outputs an inverted clock signal to the inverted clock input terminal of the processor 2a. , 6 is an exclusive NOR gate (hereinafter referred to as ENR) into which the frequency-divided signals of both processors 1a and 1b are input, 7
is a first flip-flop to which the output signal of ENR5 is inputted to the data input terminal d, and a clock signal is inputted to the trigger input terminal tr. 8 is a first AND gate to which a clock signal is input to one input terminal, and the output signal of the Q output terminal q of the flip-flop 7 is input to the other input terminal, and the output signal is input to the clock input terminal of the processor 2b. Output to ia. Reference numeral 9 represents a frequency division signal control circuit consisting of an ENR 6, a flip-flop 7 and an AND gate 8. Reference numeral 10 represents a second inverter which inverts the output signal of the Q output terminal q of the flip-flop 7 and outputs it to the inverted clock input terminal of the processor 2b.

Furthermore, 11 is a first NOR gate whose input terminal is connected to the frequency-divided output terminal oa of both processors 2a and 2b, and 12 is a second flip-flop whose trigger input terminal tr receives the output signal of the NOR gate 11. Output terminal q is connected to both processors 1
It is connected to the reset input terminal ib of each of terminals a and 1b. 13 is a reset control circuit consisting of a NOR gate 11 and a flip-flop 12; 14 is a reset section having a Schmitt circuit 15;
The output terminal of the Schmitt circuit 15 is connected to the data input terminal d and the clear terminal cl of the flip-flop 12, and the input terminal of the Schmitt circuit 15 is grounded via the reset switch 16.
It is connected to the power supply terminal Vc via a resistor 17.
A capacitor 18 is provided in parallel with the switch 16, a time constant circuit is formed by the resistor 17 and the capacitor 18 when the power is turned on, and a diode 19 is provided in parallel with the resistor 17.

Then, when the power is turned on, _the clock oscillator 4 starts operating, and as shown in _{FIG .}
hour, t ₄ o'clock, t ₅ o'clock, ... "0" to "1" respectively
A clock signal with a period Ta that changes as shown in FIG. Then, an inverted clock signal is inputted from the inverter 5 to the inverted clock input terminal of the processor _2a , and as shown in _FIG . At the same time, at t ₃ ′,
At time _t5 ', a frequency-divided signal with a period Tb that inverts from "1" to "0" is output to each of them.

On the other hand, at times t ₁ and t ₂ , the logic level of the frequency division signal of the processor 2a is "0", and as shown in FIG. 2c, the frequency division output terminal of the processor 2b is
The logic level of the frequency division signal output from oa is also “0”
Therefore, both frequency-divided signals of "0" are input to ENR6, and since the logic levels of both frequency-divided signals match, the output signal of ENR6 becomes "1".

Then, the flip-flop 7 is triggered by the rise of the clock signal from "0" to "1" at each of t ₁ o'clock, t ₂ o'clock, t ₃ o'clock, t ₄ o'clock, t ₅ o'clock, etc., and the data is transmitted to the data input terminal d. Since the output signal of ENR6 is held in flip-flop 7,
At time _t1 and time _t2 , an output signal of "1" is output from the Q output terminal q of the flip-flop 7 to the AND gate 8.

Therefore, as shown in FIG.
The clock signal is inputted to the clock input terminal ia of the processor 2b, and the clock signal passed through the AND gate 8 is inverted by the inverter 10, and the inverted clock signal obtained by inverting the clock signal is inputted from the inverter 10 to the inverted clock input terminal of the processor 2b. A frequency-divided signal is about to be output from the frequency-divided output terminal oa of the processor 2b.

However, since the formation timing of the frequency division signal of the processor 2a and the formation timing of the frequency division signal of the processor 2b are different, at time _t3 , the logic of the frequency division signal of the processor 2a is changed as shown in FIG. 2b and c, respectively. As the level becomes "1", the logic level of the frequency division signal of the processor 2b becomes "0",
The output signal of ENR6 becomes “0”.

Therefore, at _t3 , the output signal of the Q output terminal q of the flip-flop 7 becomes "0", and as shown in FIG. 2d, during one period of the clock signal from _t3 to _t4 , ANDGATE 8 to PROCESSOR 2
The clock signal to processor 2 is cut off, and
The frequency-divided signal b is held at "0".

As shown in FIG. 2b, at time t ₄ , the frequency-divided signal of the processor 2a becomes "0", and the logic level of the frequency-divided signal of the processor 2a matches that of the frequency-divided signal of the processor 2b. , same figure d
As shown in FIG.
The clock signal is output again to b and c. At this time, the timing of forming the frequency-divided signal of the processor 2a and the timing of forming the frequency-divided signal of the processor 2b are synchronized with the clock signal. As shown, both frequency-divided signals change in the same phase after _t4 .

On the other hand, when the power is turned on, the input of the Schmitt circuit 15 becomes "0", so the Schmitt circuit 15 is turned off for a predetermined time determined by the resistor 17, the capacitor 18, and the Schmitt circuit 15, as shown in FIG. 2e.
Since the output signal of the Schmitt circuit 15 is held at "0" and the output signal of the Schmitt circuit 15 is "0", the flip-flop 12 is cleared and as shown in FIG.
The output signal of the Q output terminal q of the flip-flop 12 is held at "0", and a reset signal of "0" is input to the reset input terminals ib of both processors 1a and 1b. Note that the above-mentioned predetermined time is set to a time that is sufficiently longer than the time it takes for the phases of both frequency-divided signals to match.

Then, after a predetermined period of time has elapsed, as shown in FIG. 2e, the output signal of the Schmitt circuit 15 changes from "0" to "1" at time _tx after time _t5 , and the reset of the flip-flop 12 is released. and b, c in the same figure.
As shown in each figure, the output signal of the NOR gate 11 changes from "0" to "1" due to the initial change of both frequency-divided signals from "1" to "0" at time t _y ' after time _t x. However, the flip-flop 12 is triggered, and at this time, the "1" output signal of the Schmitt circuit 15 is input to the data input terminal d of the flip-flop 12, so as shown in FIG.
At time _tz, the output signal of the Q output terminal q of the flip-flop 12 becomes "1", and both processors 2a and 2b
The reset signals of 2a and 2a in FIG.
The reset signal of processor 2b is cut off at the same time, and as shown in FIG.
t _z ' after the reset signals of a and 2b are finally cut off
Sometimes, when both frequency-divided signals change from "0" to "1" at the same time, a break in the reset signal is detected in synchronization with the change of both frequency-divided signals from "0" to "1".
Both microprocessors 2a and 2b simultaneously start executing the input program from the beginning.

Note that when the reset switch 16 is operated, both processors 2 are reset by the same operation as described above.
The reset signals of processors 2a and 2b are cut off at the same time, and both processors 2a and 2b start executing the program from the beginning at the same time.

That is, the frequency division signal control circuit 9 controls the frequency division signal only when the frequency division signals of both computers 1a and 1b simultaneously become "0" and "1", respectively, based on the timing at which the frequency division signal is formed by the frequency division circuit of the computer 1a. , a clock signal is input to the computer 1b, and the timing of forming the frequency-divided signal of 1b is made to match the timing of forming the frequency-divided signal of the computer 1a, so that the operation control timings of both computers 1a and 1b are made to match.

In addition, the reset control circuit 13 resets both computers 1 when the power is turned on and when a reset operation is performed.
After the formation timings of the frequency-divided signals of a and 1b coincide, a reset signal is sent to both computers 1a and 1b at the timing when the frequency-divided signals of both computers 1a and 1b change from "1" to "0" at the same time. Then, the resets of both computers 1a and 1b are canceled at the same timing synchronized with the frequency division signal, so that the operation start points of both computers 1a and 1b are made to coincide.

Furthermore, in FIG. 1, 20 is an external device having first to third command output terminals oe, of, og, and both peripheral devices 3a, 3 are connected to the command output terminal oe.
An interrupt command signal of "1" is output to the command input terminal if of b, and both peripheral devices 3 are output from the command output terminal of.
A hold command signal of "1" is outputted to the command input terminals ig of the peripheral devices a and 3b, and a ready command signal of "1" is outputted from the command output terminal og to the command input terminals ih of both the peripheral devices 3a and 3b. 21 is a second AND gate whose input terminal is connected to the command output terminal ob of both peripheral devices 3a, 3b;
When interrupt command signals are simultaneously input from each of 3b, the output signal becomes "1". The input terminal of 22 is the command output terminal of both peripheral devices 3a and 3b.
This is a third AND gate connected to oc, and its output signal becomes "1" when hold command signals are simultaneously input from both peripheral devices 3a and 3b. 23 is a fourth AND gate whose input terminal is connected to the command output terminal od of both the peripheral devices 3a and 3b, and when the ready signals are simultaneously input from both the peripheral devices 3a and 3b, the output signal becomes "1". become.

In addition, input terminals 24 and 25 are connected to both processors 2 and 25.
A second NOR gate and a fifth AND gate are connected to the divided output terminals oa of the processors 2a and 2b, and the output signal of the NOR gate 24 is The output signal of the AND gate 25 becomes "1" only when the frequency-divided signals of both processors 2a and 2b simultaneously become "1". 26 is a third flip-flop whose trigger input terminal tr is connected to the output terminal of the NOR gate 24, whose data input terminal d is connected to the output terminal of the AND gate 21, and whose Q output terminal q is connected to the output terminal of the AND gate 21. Connected to command input terminal IC. 27 is the trigger input terminal tr
is a fourth flip-flop connected to the output terminal of the NOR gate 24, and the data input terminal d is connected to the output terminal of the AND gate 22.
A Q output terminal q is connected to command input terminals id of both processors 2a and 2b. 28 is a fifth flip-flop whose trigger input terminal t is connected to the output terminal of the AND gate 25, and whose data input terminal d is connected to the output terminal of the AND gate 25.
is connected to the output terminal of the AND gate 23, and the Q output terminal q is connected to the command input terminal ie of both processors 2a and 2b. 29 is a command signal control circuit consisting of a NOR gate 24, an AND gate 25, and flip-flops 26-28.

For example, a command output terminal of the external device 20
When an interrupt command signal is output from oe, the command signal is input to the AND gate 21 via both peripheral circuits 3a and 3b, and at this time, the interrupt command signals via both peripheral circuits 3a and 3b are input simultaneously. The output signal of the AND gate 15 becomes "1" only during the period when the hold command signal,
Even when each ready command signal is output, the AND gate 22 is activated only while the hold command signals via both peripheral circuits 3a and 3b are simultaneously input.
The output signal of becomes “1”, and both peripheral circuits 3a, 3
The output signal of the AND gate 23 becomes "1" only while the ready command signals are simultaneously input through the terminals b, and the output signal from the peripheral circuits 3a and 3b is determined based on the error in signal transmission time between the computers 1a and 1b. The deviation in the output timing of each command signal is corrected.

Furthermore, only when the frequency-divided signals of both processors 2a and 2b become "0" at the same time, the output signal of the NOR gate 24 becomes "1", and the flip-flops 26 and 27 change the output signal of the NOR gate 24 from "0" to "1". ”, so when the divided signals of both processors 2a and 2b change from “1” to “0” at the same time, the interrupt command signal transmitted to the data input terminal d of each of the flip-flops 26 and 27 , hold command signals are held in flip-flops 26 and 27, respectively, and the flip-flops 26 and
27 outputs an interrupt command signal and a hold command signal to both processors 2a and 2b, respectively, and outputs them to both processors 2a and 2b at the same timing when the divided signals of both processors 2a and 2b change from "1" to "0". An interrupt command signal and a hold command signal are respectively sent.

Further, only when the frequency-divided signals of both processors 2a and 2b become "1" at the same time, the output signal of the AND gate 25 becomes "1", and the flip-flop 28 changes the output signal of the AND gate 25 to "0".
Since it is triggered at the rising edge of “1” from
When the ready command signal changes from "1" to "1", the ready command signal transmitted to the data input terminal d of the flip-flop 28 is held in the flip-flop 28, and the ready command signal is transmitted from the flip-flop 28 to both processors 2.
A ready signal is output to processors 2a and 2b, and a ready command signal is transmitted to both processors 2a and 2b at the same timing when the frequency-divided signals of both processors 2a and 2b change from "0" to "1".

In other words, the 8085A processor takes in the interrupt command signal and the hold command signal when the frequency division signal is "1", and the ready command signal when the frequency division signal rises from "0" to "1", so the NAND gate 24 and AND gate 25, both processors 2a, 2b
When the formation timings of the frequency-divided signals of both processors 2a and 2b coincide and the frequency-divided signals of both processors 2a and 2b change from "1" to "0" at the same time, the flip-flops 26,
27, and when the frequency-divided signals of both processors 2a and 2b change from "0" to "1" at the same time, the flip-flop 28 is triggered, and both processors synchronize with the frequency-divided signals after the formation timings match. An interrupt command signal, a hold command signal, and a ready command signal are respectively sent to the computers 1a and 2b, and both computers 1a and 1b are interrupted at the same timing and are made to take in the hold and ready operation command signals.

Therefore, according to the embodiment, the timings of forming the frequency division signals for controlling the operation timings of both computers 1a and 1b are matched by the frequency division signal control circuit 9, and the internal operation timings of both computers 1a and 1b are the same. In addition to being controlled by
Both computers 1a and 1b are reset simultaneously by the reset control circuit 13, and the operation start points of both computers 1a and 1b coincide. Furthermore, the command signal control circuit 29 transmits the interrupt command signal, hold command signal, and ready command signal output from the external device 20 to both computers 1a and 1b at the same timing synchronized with the frequency division signal after the formation timings match. It is possible to synchronize the machine cycles of computers 1a and 1b, and it is possible to operate both computers 1a and 1b accurately in parallel and synchronously with a simple circuit.
A and 1b constitute a parallel redundant system, allowing rapid and accurate failure detection and failure processing.

Moreover, by providing the AND gates 21 to 23, the deviation in the output timing of each command signal from the peripheral devices 3a and 3b, which is based on the deviation in signal transmission time between the computers 1a and 1b, is corrected.

It goes without saying that the present invention can be applied to computers having microprocessors other than the 8085A type microprocessor of the embodiment described above, as well as computers having no peripheral devices.

Also, as the number of computers increases,
While increasing the number of frequency division signal control circuits 9,
The NOR gate 11 of the reset control circuit 13 may be formed of a multi-input type NOR gate, and the NOR gate 24 and AND gate 25 of the command signal control circuit 29 may be formed of a multi-input type NOR gate and an AND gate, respectively.

[Brief explanation of the drawing]

The drawings show one embodiment of the parallel synchronous operation control device of the present invention, FIG. 1 is a block diagram of the main parts, and FIGS. 2a to 2f are timing charts for explaining the operation of FIG. 1. 1a, 1b...Microphone computer, 4...Clock generator, 9...Frequency division signal control circuit, 13...
...Reset control circuit, 20... External device, 29...
...Command signal control circuit.

Claims (1)

[Claims] 1 A plurality of microcomputers which divide the input clock signal by a built-in frequency dividing circuit to form a divided signal for operation timing control, and A frequency division signal control circuit that synchronizes the formation timing of the frequency division signals of each computer, and a frequency division signal control circuit that simultaneously interrupts the reset of each of the computers after the formation timing of the frequency division signals coincides with each other, and a time point at which each of the computers starts operating. and a command signal control circuit that causes various operation command signals of external devices to be input into each of the computers in synchronization with the frequency-divided signal after the formation timings match. Parallel synchronous operation control device.