JPS6366429B2 - - Google Patents
Info
- Publication number
- JPS6366429B2 JPS6366429B2 JP56073182A JP7318281A JPS6366429B2 JP S6366429 B2 JPS6366429 B2 JP S6366429B2 JP 56073182 A JP56073182 A JP 56073182A JP 7318281 A JP7318281 A JP 7318281A JP S6366429 B2 JPS6366429 B2 JP S6366429B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- emitter region
- shaped
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は同一半導体片内にベース、エミツタ間
挿入抵抗およびフローテイングエミツタを備えた
トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor having a base, an emitter-to-emitter inserted resistor, and a floating emitter in the same semiconductor piece.
トランジスタの安定化のために第1図に示すよ
うにベース、エミツタ間に接続される抵抗Rをト
ランジスタと同一半導体片内に拡散抵抗として形
成することがある。一方、トランジスタのASO
(安全動作領域)特性向上のためにエミツタを囲
んでエミツタと同一導電形を示す環状領域、いわ
ゆるフローテイングエミツタを形成することがあ
る。第2図はこの両者を備えたトランジスタを示
し、N形のシリコン板1に拡散法によつて先ずP
形ベース領域2が形成され、さらにその中にN形
エミツタ領域3が形成されている。エミツタ領域
3のほぼ全周を囲んでそれより幅の狭いN形のほ
ぼ環状の帯状領域4がフローテイングエミツタと
して、さらに一端がエミツタ領域3につながりや
はりそれより幅の狭いN形帯状領域5が例えばエ
ミツタ領域の形成を同一の拡散工程によつて形成
されている。帯状領域5の他端6はベース領域2
を覆う図示しない電極に接続されるので、帯状領
域5は第1図のRに相当するエミツタ、ベース間
に挿入された抵抗となる。しかしこの場合フロー
テイングエミツタは完全な環状を形成せず、また
帯状領域5もエミツタとして作用するためフロー
テイングエミツタの効果の存在しないエミツタ領
域3と帯状領域5の結合部付近から二次降伏を起
こしやすい欠点があつた。この欠点を解消するた
め第3図に示すように抵抗となるN形帯状領域5
をエミツタ領域3と離して形成し、エミツタ領域
3をフローテイングエミツタ4で完全に囲み、さ
らに帯状領域5を完全に囲んだN形環状領域9を
設けたものが提案されている。この帯状領域5は
ベース領域2およびエミツタ領域3と環状領域9
または4を絶縁膜を介して越える金属電極7およ
び8によつて接続されている。しかしこのような
構造にしてもエミツタ領域3あるいは帯状領域5
の接続電極8との結合部付近で二次降伏が起りや
すく、その結果良好な破壊耐量を有するものが得
られなかつた。 In order to stabilize the transistor, as shown in FIG. 1, the resistor R connected between the base and the emitter is sometimes formed as a diffused resistor in the same semiconductor piece as the transistor. On the other hand, transistor ASO
(Safe operation area) In order to improve the characteristics, a so-called floating emitter, which is an annular region surrounding the emitter and exhibiting the same conductivity type as the emitter, is sometimes formed. FIG. 2 shows a transistor equipped with both of these elements.
A shaped base region 2 is formed, furthermore an N-type emitter region 3 is formed therein. An N-shaped, almost annular strip region 4 that surrounds almost the entire circumference of the emitter region 3 and is narrower than the emitter region 3 serves as a floating emitter, and furthermore, one end is connected to the emitter region 3 and an N-shaped strip region 5 that is also narrower than the emitter region 3 is formed as a floating emitter. For example, the emitter region is formed by the same diffusion process. The other end 6 of the strip area 5 is the base area 2
Since the band-shaped region 5 is connected to an electrode (not shown) covering the surface, the band-shaped region 5 becomes a resistor inserted between the emitter and the base corresponding to R in FIG. However, in this case, the floating emitter does not form a perfect ring shape, and the strip region 5 also acts as an emitter, so secondary breakdown occurs near the joint between the emitter region 3 and the strip region 5, where the effect of the floating emitter does not exist. There was a drawback that it was easy to cause this. In order to eliminate this drawback, as shown in FIG.
It has been proposed that the emitter region 3 is formed separately from the emitter region 3, the emitter region 3 is completely surrounded by floating emitters 4, and an N-shaped annular region 9 that completely surrounds the strip region 5 is provided. This band-shaped region 5 includes a base region 2, an emitter region 3, and an annular region 9.
Alternatively, the metal electrodes 7 and 8 are connected to each other through an insulating film. However, even with this structure, the emitter region 3 or the strip region 5
Secondary breakdown was likely to occur near the joint with the connecting electrode 8, and as a result, it was not possible to obtain a material with good breakdown resistance.
本発明は同一半導体片内にベース、エミツタ間
挿入抵抗を有し、かつ良好な破壊耐量を示すトラ
ンジスタを提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a transistor that has a resistance inserted between a base and an emitter in the same semiconductor piece and exhibits good breakdown resistance.
この目的はベース領域内にエミツタ領域と、一
端がエミツタ領域に連結され他端がベース領域と
接続されるエミツタ領域と同一導電形であるがそ
れより小さい横断面を持つ第一の帯状領域と、同
様にエミツタ領域と同一導電形でエミツタ領域の
外周および少なくともエミツタ領域との連結端に
近い第一の帯状領域の外周を間隔を介して取り囲
む第二の帯状領域とを設けることによつて達成さ
れる。 This purpose includes an emitter region in the base region, a first strip region of the same conductivity type as the emitter region but with a smaller cross-section, which is connected at one end to the emitter region and at the other end to the base region; Similarly, this can be achieved by providing a second band-like region which is of the same conductivity type as the emitter region and surrounds the outer periphery of the emitter region and at least the outer periphery of the first strip-like region near the connecting end with the emitter region, with a gap therebetween. Ru.
以下図を引用して本発明の実施例について説明
する。第4図において、第2図におけると同様N
形シリコン板1にP形ベース領域2が形成され、
さらにその中にN形エミツタ領域3が形成されて
いる。また一端がエミツタ領域3につながりそれ
より幅の狭いN形帯状領域5が形成されている。
第2図と異なる点はエミツタ領域3を取り囲むほ
ぼ環状の帯状領域4が、エミツタ領域3の外周だ
けでなく他端6においてベース領域2と接続され
てベース、エミツタ間挿入抵抗として役立つ帯状
領域5の外周に沿つて延びている。このフローテ
イングエミツタとして働く帯状領域4は抵抗領域
5の外周を完全に包囲してもよいが、図示のよう
にそのエミツタ領域3との連結場所に近い部分に
設けられるだけでトランジスタの破壊耐量が著し
く改善される。 Embodiments of the present invention will be described below with reference to the drawings. In Figure 4, as in Figure 2, N
A P-shaped base region 2 is formed on a shaped silicon plate 1,
Furthermore, an N-type emitter region 3 is formed therein. Further, one end is connected to the emitter region 3, and an N-shaped strip region 5 having a narrower width than the emitter region 3 is formed.
The difference from FIG. 2 is that a substantially annular band-shaped region 4 surrounding the emitter region 3 is connected to the base region 2 not only at the outer periphery of the emitter region 3 but also at the other end 6, and serves as a resistance for insertion between the base and the emitter region 5. It extends along the outer periphery of the The band-shaped region 4, which functions as a floating emitter, may completely surround the outer periphery of the resistor region 5, but as shown in the figure, if it is provided only in a portion close to the location where it is connected to the emitter region 3, the breakdown resistance of the transistor will be increased. is significantly improved.
以上述べたように本発明はトランジスタのベー
ス、エミツタ間挿入抵抗としてベース領域に形成
されるエミツタ領域と同一導電形の帯状領域の一
端をエミツタ領域と連結し、エミツタ領域および
帯状領域の少なくともエミツタ領域との連結端に
近い部分の外周を取り囲んでフローテイングエミ
ツタを設けるものである。本発明によるトランジ
スタにはエミツタ領域とほぼ同電位でフローテイ
ングエミツタに囲まれない帯状抵抗領域の端部あ
るいはエミツタ領域との接続電極が存在しないた
め二次降伏が起り難くなり、破壊耐量が向上す
る。またフローテイングエミツタは必ずしも抵抗
領域の全周を囲む必要がないため、抵抗領域の周
りにフローテイングエミツタを設けない場合に比
しての面積の増加を僅かにすることも可能であ
る。 As described above, the present invention connects one end of a strip-shaped region of the same conductivity type as the emitter region formed in the base region as a resistance inserted between the base and emitter of a transistor to the emitter region, and at least the emitter region of the emitter region and the strip-shaped region. A floating emitter is provided surrounding the outer periphery of the portion near the connection end. In the transistor according to the present invention, since there is no end of the band-shaped resistance region that is at almost the same potential as the emitter region and is not surrounded by the floating emitter or a connecting electrode with the emitter region, secondary breakdown is less likely to occur and the breakdown resistance is improved. do. Furthermore, since the floating emitter does not necessarily need to surround the entire circumference of the resistance region, it is possible to minimize the increase in area compared to the case where no floating emitter is provided around the resistance region.
第1図は本発明の対象であるトランジスタの回
路図、第2図、第3図は従来のトランジスタの二
つの例をそれぞれ示す平面図、第4図は本発明の
実施例を示す平面図である。
2…ベース領域、3…エミツタ領域、4…(フ
ローテイングエミツタ)帯状領域、5…(抵抗)
帯状領域。
FIG. 1 is a circuit diagram of a transistor that is the object of the present invention, FIGS. 2 and 3 are plan views showing two examples of conventional transistors, and FIG. 4 is a plan view showing an embodiment of the present invention. be. 2... Base region, 3... Emitter region, 4... (Floating emitter) strip region, 5... (Resistance)
zonal area.
Claims (1)
ツタ領域に連結され他端がベース領域に接続され
たエミツタ領域と同一導電形であるがそれより小
さい横断面を持つ第一の帯状領域と、同様にエミ
ツタ領域と同一導電形でエミツタ領域の外周およ
び少なくともエミツタ領域との連結端に近い第一
の帯状領域の外周を間隔を介して取り囲む第二の
帯状領域とを設けたことを特徴とするトランジス
タ。1 an emitter region in the base region; a first strip region of the same conductivity type as the emitter region but with a smaller cross section, connected at one end to the emitter region and at the other end to the base region; A transistor characterized in that it is provided with a second band-shaped region having the same conductivity type as the emitter region and surrounding the outer periphery of the emitter region and at least the outer periphery of the first band-shaped region near the connection end with the emitter region with a gap therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56073182A JPS57188869A (en) | 1981-05-15 | 1981-05-15 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56073182A JPS57188869A (en) | 1981-05-15 | 1981-05-15 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57188869A JPS57188869A (en) | 1982-11-19 |
| JPS6366429B2 true JPS6366429B2 (en) | 1988-12-20 |
Family
ID=13510735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56073182A Granted JPS57188869A (en) | 1981-05-15 | 1981-05-15 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57188869A (en) |
-
1981
- 1981-05-15 JP JP56073182A patent/JPS57188869A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57188869A (en) | 1982-11-19 |
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