JPS637092A - video storage device - Google Patents

Abstract

PURPOSE:To eliminate a hue error which may occur due to outrunning by inserting status information by a block unit corresponding to the phase information of a video signal on an input side, discriminating it on an output side to detect passing and inverting the phase information of the video signal from the time when the passing occurs. CONSTITUTION:In an encoder 20 input data series and status information are sampling-converted to change the series, namely, the input data series is com pressed in terms of time base and in a gap part issued by a said compression the status information is inserted to form the data. The data is transferred to a memory 5A through buffers 2A and 3A and then transferred to buffers 9A and 10A. And in a decoder 21 the data from 9A and 10A is sampling- converted again to obtain the continuous data series, that is, the data is expand ed in terms of time base to be the former data series and at the same time the status information is fetched by a block unit. The fetched status information is checked in a status order discrimination circuit 22 and whether it is the same as the status information inserted on the encoder side is decided and if they are not same, it is decided that passing occurs, so the phase of the video signal after that is inverted in a chroma invertor 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video storage device suitable for use in image processing in, for example, video tape recorders, television receivers, and the like.

[Summary of the invention]

This invention provides a video storage device that performs image processing in a video tape recorder, television receiver, etc., in which input data strings and status information are sampled, converted, rearranged, and written into memory means, and signals read out from the memory means. is sampled and converted again to obtain a continuous data string, at the same time extracting the status information in block units, comparing and determining the extracted status information with the status information at the time of input, and depending on the determination result, phase information of the output of the memory means is determined. By correcting this, hue errors due to overtaking are prevented from occurring.

[Conventional technology]

As a conventional video storage device that performs image processing, for example,
As shown in the figure, an asynchronous FIFO type memory having a plurality of serial access memories (hereinafter referred to as SAMs) each having a capacity smaller than that of an IH has been proposed. That is,
In FIG. 4, data from the input terminal (1) is written to a predetermined position of the write SAM (21 and (3)) of equal capacity, for example, N1 bits, based on the write clock signal CKW.SAM (2) The data written in (3) is selectively taken out by the switch circuit (4) and transferred to the Guinami Sok Random Access Memory (hereinafter referred to as DR).
AM) (5). In other words, S.A.
M (S A M when writing data to 2+
(The data of SAM (31) is transferred to DRAM (51), and conversely, when data is being written to S A M (31), the data of S A M (21 is transferred to DRAM+51.

The DRAM (51 has a capacity of M lines (N x M), for example, with 1 line (corresponding to, but not limited to) N bits, and 1 line has a capacity of, for example, N
It is divided into two blocks (one block is N1 bits). (6) is an address circuit for writing, and first, the row address signal from the address circuit (6) is used to write the DRAM
A line of +51 is proposed, then an address circuit (
Column address signal from DRAM (5)
block) is designated, and N1 bit data from S A M (21 or (3)) is written to the specified predetermined position.

(7) is an address circuit for reading, and first, a row address signal from the address circuit (7) is sent to [ll? l1
The row (line) of M (51) is specified, and then the column (block) of the DRAM (5) is specified by the column address signal from the address circuit (6), and the data is written to the specified predetermined position. The data of N1 pinto is read.

(8) is a switch circuit, (9) and (10) are S A
M (Read SA with capacity equal to 21 and (3)
M, (11) is an output terminal, and address circuit (7)
The data of N1 bits at a predetermined position in the DRAM (5) specified by the row address signal and column address signal from S A is read out and taken out by the S inch circuit (8).
The data from DRAM (51) is selectively transferred to S A M (91 or (10)).
When the data is being transferred to the DRAM+, the data written to the SAM (10) is read out based on the read clock signal CKH and output to the output terminal (11), and conversely, the data written to the SAM (10) is
When data from SAM 51 is being transferred to SAM (10), data written in SAM (91) is read out based on read clock signal CKR and output to output terminal (11).

In addition, from S A M (2) and (3), DRAM (5
1 and from DRAM+51 to S A M (91
When transfers to and (lO) conflict, priorities are assigned and the transfer timings are shifted from each other.

[Problem that the invention seeks to solve]

By the way, in the configuration shown in FIG. 4, since the input and output are asynchronous, the write address signal from the address circuit (6) and the read address signal from the address circuit (7) will overtake each other somewhere, and this At the time of overtaking, inconveniences occur such as data being replaced from the current field to the previous field.

That is, for example, if the write address signal precedes the read address in the 5[1] and their frequencies are equal, overtaking will not occur, so the row address signal from the address circuit (6)
One line is specified, N2 blocks from θ to N2-1 are sequentially specified using the column address signal and data is written, and the row address signal from the address circuit (7) is used to write data into the DRAM+5.
1 m1 line is specified, and θ~N2 is specified by the column address signal.
-1 N2 blocks are sequentially designated and written data is read out.

However, if the frequency of the read address signal is higher than the frequency of the write address signal when the write address signal precedes the read address signal, for example, the readout occurs at the boundary between the nth and fi+1th blocks. The write address signal begins to catch up with the write address signal, and a phenomenon of overtaking occurs. At this time, the write cycle and column address signals and the read cycle and column address circuits are in agreement, respectively.

Then, the information of the current field is read from the 0th to nth blocks before the overtaking occurs, but the previous field information is read from the n+1st to N2-1th blocks after the overtaking occurs. Therefore, the current field information and the previous field information are mixed in one line, resulting in a hue error on the screen.

Also, when the read address signal precedes the write address signal and the frequency of the write address signal is higher than the frequency of the read address signal,
For example, at the boundary between the n-th and fi+1-th blocks, the write address signal catches up with the read address signal, and an overtaking phenomenon occurs here. At this time, the row and column address signals for writing and the row and column address signals for reading are in agreement, respectively.

Then, the previous field information is read in the 0-nth blocks before the overtaking occurs, but the current field information is read out in the n+1th to N2-1th blocks after the overtaking occurs. In this case as well, the previous field information and the current field 1' information are mixed in one line, resulting in a hue error on the screen.

The present invention has been made in view of the above, and an object of the present invention is to provide a video storage device that can eliminate hue errors caused by overtaking.

[Means for solving problems]

The video storage device according to the present invention uses an encoder (
20) and a buffer (2Al,
(3A), memory means (5^) to (7A) having a plurality of (98 and (IOA)) in the input/output section, and the output of this memory means is sampled and converted again to obtain a continuous data string and at the same time block It is equipped with a decoder (21) for extracting status information in units, and a discrimination circuit (22) for comparing and discriminating the status information in the encoder and the status information in the decoder, and depending on the output of the discrimination circuit, the phase of the output of the memory means is determined. Correct information (23)
It is configured to do so.

[Effect]

In the encoder (20), the input data string and the status information are sampled, converted, and rearranged, that is, the input data string is compressed on the time axis, and the status information is inserted into the resulting gap to form data. This data is
A M (24) and (3Ayc) are transferred to the DRAM (2), and further transferred to S A M (9A) and (10A). Then, in the decoder (21), S A M
The data from (9A) and (IOA) are sampled and converted again to obtain a continuous data string, that is, the time axis is expanded and returned to the original data string, and at the same time, status information is extracted in block units. The retrieved status information is checked by the discrimination circuit (22) to see if it is the same as the status information inserted on the encoder side. If it is not the same, it is assumed that overtaking has occurred, and the subsequent video signal (sub The phase of the carrier) is inverted by a chroma inverter (23). This eliminates hue errors caused by overtaking.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows the circuit configuration of this embodiment. In the figure, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, input terminal (1), SAM (2A) and (3
An encoder (20) is provided between 8). Encoder (
20) samples and converts the 1-bit status information as shown in Figure 2A and the N1-bit input data string from the input terminal (1) as shown in Figure 2B, and converts it as shown in Figure 2C. rearrange. That is, the encoder (20) compresses the N1-bit input data string on the time axis in units of blocks, inserts 1-bit status information at a predetermined position in the resulting gap, for example, at the beginning position, and outputs it. As for the status information, we focused on the fact that the phase information of the subcarrier (burst) is inverted every 1I4, and set this to "1".
.

, 10 is used in correspondence with a logic signal of "0". For example, "0" if the subcarrier starts from the positive phase at the beginning of one line, and "1" if the subcarrier starts from the negative phase.
correspond. Therefore, the same logic signal is assigned to each block of one line. It should be noted that the status information does not necessarily need to be written to the first address of each block, and may be written to any address in consideration of the inversion timing in the chroma inverter (23), which will be described later.

By adding 1-bit status information to the N1-bit input data string, one block becomes N1+1 bits, and therefore SAM (2A).

The capacity of (3A) and (9A), <IOA) is N
+1 bit. Also, the answer to this is DNA
For example, (5A) has a capacity of M lines (N'×M) with one line being N' focus, and one line is divided into N2 blocks (one block is N units→-1 bit).

Further, a decoder (21) is provided on the output side of the SAMs (9A) and (10^), and the video signal and status information are separated here. That is, SAM(9A) and (IOA)
From there, data in which status information is inserted into an input data string as shown in FIG. 3A is supplied to the decoder (21), and the decoder (21) uses this input information to generate data as shown in FIG. 3B. (video signal) and status information as shown in FIG. 3C are separated and output. The separated status information is supplied to a status order determining circuit (22), and the video signal is sent to a chroma inverter (23).

In the status order determination circuit (22), the decoder (21)
It is checked whether the status information from the encoder (20) is arranged according to the rules inserted. For example, when there is no overtaking, the status information detected by the discrimination circuit (22) is in the logic signal inserted on the encoder (20) side, but when overtaking occurs, the phase information of the subcarrier is reversed; Accordingly, the discrimination circuit (22
) The status information detected by the overtaking occurs when the logic signal changes from “0” to “1” or from
” and changes to another logic signal. This change occurs in block units because the status information is inserted in block units.

Therefore, when the determination circuit (22) determines that the status information has changed, it is determined that overtaking has occurred.
A control signal is supplied to the chroma inverter (23) to invert the phases of the subcarriers from then on. This eliminates hue errors due to overtaking.

Note that the encoder (20) and decoder (21) can be built into the memory if the number of pins is sufficient.

〔Effect of the invention〕

As described above, according to the present invention, overtaking is detected by inserting status information block by block corresponding to the phase information of the video signal (subcarrier) on the input side and determining this on the output side. Since the phase information of the video signal is inverted from the point at which it occurs, there is no hue error due to overtaking, and there is no need to provide a dedicated overtaking detection circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the present invention,
FIG. 4 is a circuit configuration diagram showing an example of a conventional device, and FIG. 5 is a diagram for explaining an overtaking operation. (2A), (3A), (9^), (IOA
) is serial access memory (SAM), (58) is random access memory (DRAM),
(6A). (7^) is the address circuit, (20) is the encoder, (2
1) is a decoder, (22) is a status order determination circuit,
(23) is a chroma inverter.

Claims (1)

[Scope of Claims] An encoder that samples and converts and rearranges input data strings and status information, and a memory means having a plurality of buffers in an input/output section each having a capacity equivalent to the number of bits per block rearranged by the encoder. , a decoder that resamples and converts the output of the memory means to obtain a continuous data string and at the same time extracts status information in block units, and a discrimination circuit that compares and discriminates the status information in the encoder and the status information in the decoder, A video storage device characterized in that the phase information of the output of the memory means is corrected by the output of the discrimination circuit.