JPS6410492A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6410492A
JPS6410492A JP62164545A JP16454587A JPS6410492A JP S6410492 A JPS6410492 A JP S6410492A JP 62164545 A JP62164545 A JP 62164545A JP 16454587 A JP16454587 A JP 16454587A JP S6410492 A JPS6410492 A JP S6410492A
Authority
JP
Japan
Prior art keywords
power supply
data line
recovery time
data lines
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62164545A
Other languages
Japanese (ja)
Inventor
Akitoshi Tetsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62164545A priority Critical patent/JPS6410492A/en
Publication of JPS6410492A publication Critical patent/JPS6410492A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To decrease the write recovery time of a static (S) RAM by controlling the electric conduction of a transistor connected between a common data line and a power supply in a prescribed timing to charge the common data line quickly. CONSTITUTION:A pulse generator 24 generates a control signal phi for a prescribed time only after the rising of a write signal to turn on pull-up FETs 7a, 7b connected respectively between command data lines 1a, 1b and the power supply. Thus, the data lines 1a, 1b are charged quickly to reduce the write recovery time of the SRAM considerably.
JP62164545A 1987-07-01 1987-07-01 Semiconductor storage device Pending JPS6410492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62164545A JPS6410492A (en) 1987-07-01 1987-07-01 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62164545A JPS6410492A (en) 1987-07-01 1987-07-01 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6410492A true JPS6410492A (en) 1989-01-13

Family

ID=15795191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62164545A Pending JPS6410492A (en) 1987-07-01 1987-07-01 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6410492A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006031767A (en) * 2004-07-13 2006-02-02 Fujitsu Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60242583A (en) * 1984-11-28 1985-12-02 Hitachi Ltd memory circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60242583A (en) * 1984-11-28 1985-12-02 Hitachi Ltd memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006031767A (en) * 2004-07-13 2006-02-02 Fujitsu Ltd Semiconductor device

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