JPS6411407A - Delay device - Google Patents

Abstract

PURPOSE:To accurately delay a signal by one field and to reduce noise of the signal by providing a variable delay circuit and also providing a phase comparator circuit which compares the phase of the output signal of the variable delay circuit with an analog input signal. CONSTITUTION:A pilot signal is inserted into the analog input signal S1 though an adder 11, a synchronizing separator circuit 12, a gate circuit 13, a clock generator 10, a phase comparator circuit 14, etc., and the resulting input signal is applied to adders 2 and 3 to obtain a signal S6 through the variable delay circuit 15, etc. The signal S6 is fed back to the adder 2 and a pilot signal S51 is extracted through a gate circuit 16 and phase-compared with the signal S5 by the circuit 14. Consequently, a phase comparison signal S7 is outputted and held by a sample hold circuit 18 through an LPF 17, and its held signal serves as a control signal S8 to control the delay quantity of the circuit 15. Then the output signal of the adder 3 is passed through an LPF 5, an A/D converter 6, a field memory 7, a D/A converter 8, etc., and then the circuit 15 to make the delay quantity accurate, thereby reducing noises.