JPS6424678A - Decoding processing system - Google Patents

Abstract

PURPOSE:To save the size of a processing circuit by using a predicted coincident run (n) and a predicted dissident run whose lenght is 1 as one processing unit at the point of time when the run length data (n) of the prediction coincident run is obtained to apply picture element reproduction at once and reproducing the picture element of the prediction dissident run only when the run length of the code of succeeding prediction dissidence is not 1. CONSTITUTION:A data transfer control section 11 receives a run length data and prediction coincidence/dissidence information, and when the prediction is coincident, the run length data is sent to an error bit pattern generating section 12 and when dissident, the data is sent to a dissidence run length discrimination section 16. The generating section 12 generates an error bit pattern comprising the received run length data (predicted coincidence bit) and one 1 (prediction dissidence bit) and sends the result to an original data bit reproduction section 13. When the received dissidence run length is 1, the discrimination section 16 executes nothing and only when the run length exceeds 1, the section 16 sends the run length data to the error bit pattern generating section 17. The generating section 17 generates the error bit pattern comprising received run length (prediction dissidence bit)-1 ( prediction dissidence bit) and sends it to a reproducing section 13. The reproducing section 13 uses the error bit pattern and the prediction data to reproduce the original data.