JPS6432351A - Cache memory control system - Google Patents

Abstract

PURPOSE:To ensure the effective application of the entire capacity of a memory by producing an address added with higher (n) bits in response to an address having 1/n<2> page size and changing successively the higher (n) bits at the time of a misbit. CONSTITUTION:In a page mode of 1/2<n>=1/2 page size with n=1, etc., the addresses of a real address part 12 stored in a logical address register 1, 1/2 page size mode signal 150 and the output of a change circuit 9 are processed by AND circuits 6 and 7 and an OR circuit 8 for production of an address added with a higher 1 bit which give accesses to a cache directory part 3 and a cache memory part 4. Then a misbit signal is outputted from a comparator 21 in case no coincidence is obtained between a real address 230 given from the part 3 and a real address given from an address conversion buffer 2. Then the output of the circuit 9 changes to 1 from 0 and the part 4, etc., receive accesses with an address having a changed higher 1 bit. Then the working page size is equal to 1/2<n> page and therefore the entire memory capacity is used effectively.