JPS6471296A - Control data/voice data transmission reception circuit - Google Patents

Control data/voice data transmission reception circuit

Info

Publication number
JPS6471296A
JPS6471296A JP22629487A JP22629487A JPS6471296A JP S6471296 A JPS6471296 A JP S6471296A JP 22629487 A JP22629487 A JP 22629487A JP 22629487 A JP22629487 A JP 22629487A JP S6471296 A JPS6471296 A JP S6471296A
Authority
JP
Japan
Prior art keywords
circuit section
data
control
sends
control data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22629487A
Other languages
Japanese (ja)
Inventor
Akira Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22629487A priority Critical patent/JPS6471296A/en
Publication of JPS6471296A publication Critical patent/JPS6471296A/en
Pending legal-status Critical Current

Links

Landscapes

  • Sub-Exchange Stations And Push- Button Telephones (AREA)

Abstract

PURPOSE:To reduce the bit rate by superimposing either a voice data or a control data onto a serial data sent during one sampling period. CONSTITUTION:A control data buffer 17 buffers a control data from a main control section and sends it to a synthesis circuit section 18. The synthesis circuit section 18 receiving it inputs a PCM voice signal 19 at the same time to synthesize and output the serial data. A driver circuit section 20 receives the serial data from the synthesis circuit section 18 and sends it to a transmission line. A reception circuit section 23 converts an input signal from a transmission line into a logic level and the synchronizing circuit section 24 synchronizes the serial data from the reception circuit section 23 and sends the result to a demultiplex circuit section 25. The demultiplex circuit section 25 demultiplexes the data part into the voice data or the control data and sends the voice data to a voice data latch circuit 26 and the control data to a telephone control section.
JP22629487A 1987-09-11 1987-09-11 Control data/voice data transmission reception circuit Pending JPS6471296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22629487A JPS6471296A (en) 1987-09-11 1987-09-11 Control data/voice data transmission reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22629487A JPS6471296A (en) 1987-09-11 1987-09-11 Control data/voice data transmission reception circuit

Publications (1)

Publication Number Publication Date
JPS6471296A true JPS6471296A (en) 1989-03-16

Family

ID=16842954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22629487A Pending JPS6471296A (en) 1987-09-11 1987-09-11 Control data/voice data transmission reception circuit

Country Status (1)

Country Link
JP (1) JPS6471296A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08240642A (en) * 1995-03-02 1996-09-17 Nec Corp Method and equipment for testing subscriber circuit card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08240642A (en) * 1995-03-02 1996-09-17 Nec Corp Method and equipment for testing subscriber circuit card

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