JPS6473446A - Direct memory access controller - Google Patents

Direct memory access controller

Info

Publication number
JPS6473446A
JPS6473446A JP23025987A JP23025987A JPS6473446A JP S6473446 A JPS6473446 A JP S6473446A JP 23025987 A JP23025987 A JP 23025987A JP 23025987 A JP23025987 A JP 23025987A JP S6473446 A JPS6473446 A JP S6473446A
Authority
JP
Japan
Prior art keywords
data
latch circuits
waiting
instruction signal
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23025987A
Other languages
Japanese (ja)
Other versions
JP2545407B2 (en
Inventor
Kokichi Taniai
Tatsuya Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23025987A priority Critical patent/JP2545407B2/en
Publication of JPS6473446A publication Critical patent/JPS6473446A/en
Application granted granted Critical
Publication of JP2545407B2 publication Critical patent/JP2545407B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To attain data transfer corresponding to the access speed of an external circuit by holding optional micro data in accordance with the instruction of a waiting instruction signal and supplying it from latch circuits to an internal circuit. CONSTITUTION:Selector circuits 33 and 39 supply again micro data which the latch circuits 34 and 35 output in accordance with the instruction of the waiting instruction signal and which delay circuits 37 and 38 have delayed for a prescribed time to the latch circuits 34 and 35. Consequently, optional data are held by latch circuits 34 and 35 which the stand-by instruction signal instructs. Micro data of a cycle T3 which terminates the internal processing of data transfer in a DMAC are instructed by the waiting instruction signal until a data complete signal in the external circuit is asserted. Thus, data is held for necessary quantity and a waiting cycle can be inserted meanwhile.
JP23025987A 1987-09-14 1987-09-14 Direct memory access controller Expired - Fee Related JP2545407B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23025987A JP2545407B2 (en) 1987-09-14 1987-09-14 Direct memory access controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23025987A JP2545407B2 (en) 1987-09-14 1987-09-14 Direct memory access controller

Publications (2)

Publication Number Publication Date
JPS6473446A true JPS6473446A (en) 1989-03-17
JP2545407B2 JP2545407B2 (en) 1996-10-16

Family

ID=16904999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23025987A Expired - Fee Related JP2545407B2 (en) 1987-09-14 1987-09-14 Direct memory access controller

Country Status (1)

Country Link
JP (1) JP2545407B2 (en)

Also Published As

Publication number Publication date
JP2545407B2 (en) 1996-10-16

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees