JPS6474737A - Master slice type semiconductor device - Google Patents

Master slice type semiconductor device

Info

Publication number
JPS6474737A
JPS6474737A JP62232907A JP23290787A JPS6474737A JP S6474737 A JPS6474737 A JP S6474737A JP 62232907 A JP62232907 A JP 62232907A JP 23290787 A JP23290787 A JP 23290787A JP S6474737 A JPS6474737 A JP S6474737A
Authority
JP
Japan
Prior art keywords
layer
power supply
potential
mos capacitor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62232907A
Other languages
Japanese (ja)
Other versions
JP2840239B2 (en
Inventor
Seiji Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62232907A priority Critical patent/JP2840239B2/en
Publication of JPS6474737A publication Critical patent/JPS6474737A/en
Application granted granted Critical
Publication of JP2840239B2 publication Critical patent/JP2840239B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the fluctuation in power supply potential on power supply line for stabilizing the potential by providing a MOS capacitor using two layer aluminum interconnections on an unused cell. CONSTITUTION:A MOS capacitor is formed between the first layer metallic interconnection layer 15 and the second layer metallic interconnection layer 18 holding an interlayer insulating film 17 on overall surface of an unused transistor of basic cell while the MOS capacitor is connected between VDD and VSS power supplies. Besides. the first layer metallic interconnection layer 15 is brought into ohmic contact with source.drain 13, 14 through the intermediary of contact holes 16 while the potential of source.drain of not yet used P channel type MOS transistor is fixed to VDD power supply. In such a constitution, a gate electrode 12 is connected to the isolated first layer metallic layer 15 through the intermediary of the contact hole 10 so that the potential of the electrode 12 may be fixed to the VSS power supply. Consequently, the structure of this transistor device is extremely resistant to latch up.
JP62232907A 1987-09-17 1987-09-17 Master slice type semiconductor device Expired - Fee Related JP2840239B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232907A JP2840239B2 (en) 1987-09-17 1987-09-17 Master slice type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232907A JP2840239B2 (en) 1987-09-17 1987-09-17 Master slice type semiconductor device

Publications (2)

Publication Number Publication Date
JPS6474737A true JPS6474737A (en) 1989-03-20
JP2840239B2 JP2840239B2 (en) 1998-12-24

Family

ID=16946709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232907A Expired - Fee Related JP2840239B2 (en) 1987-09-17 1987-09-17 Master slice type semiconductor device

Country Status (1)

Country Link
JP (1) JP2840239B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02241061A (en) * 1989-03-15 1990-09-25 Oki Electric Ind Co Ltd Cmos gate array
WO2000035004A1 (en) 1998-12-10 2000-06-15 Nec Corporation Integrated circuit
US6507232B2 (en) 1998-07-09 2003-01-14 Nec Corporation Semiconductor device which can be set to predetermined capacitance value without increase of delay time
WO2006018891A1 (en) * 2004-08-20 2006-02-23 Fujitsu Limited Semiconductor device and designing method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02241061A (en) * 1989-03-15 1990-09-25 Oki Electric Ind Co Ltd Cmos gate array
US6507232B2 (en) 1998-07-09 2003-01-14 Nec Corporation Semiconductor device which can be set to predetermined capacitance value without increase of delay time
WO2000035004A1 (en) 1998-12-10 2000-06-15 Nec Corporation Integrated circuit
WO2006018891A1 (en) * 2004-08-20 2006-02-23 Fujitsu Limited Semiconductor device and designing method therefor

Also Published As

Publication number Publication date
JP2840239B2 (en) 1998-12-24

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees