JPS6489342A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6489342A
JPS6489342A JP62245016A JP24501687A JPS6489342A JP S6489342 A JPS6489342 A JP S6489342A JP 62245016 A JP62245016 A JP 62245016A JP 24501687 A JP24501687 A JP 24501687A JP S6489342 A JPS6489342 A JP S6489342A
Authority
JP
Japan
Prior art keywords
layer
superconducting material
interconnection
region
altered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245016A
Other languages
Japanese (ja)
Inventor
Minoru Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62245016A priority Critical patent/JPS6489342A/en
Publication of JPS6489342A publication Critical patent/JPS6489342A/en
Pending legal-status Critical Current

Links

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To superpose and form many multilayer interconnection regions each having a flat structure by forming a conductive layer made of a superconducting material on a semiconductor substrate, and then selectively insulating the superconducting material except the interconnection regions. CONSTITUTION:A conductive layer 2 made of a superconducting material is formed on a semiconductor substrate 1 formed with a predetermined semiconductor element. Then, a photoresist layer 3 is formed on a section to be formed with the wiring region 6 of the layer 2. Then, energetic particles 4 are irradiated to be implanted in high density to the exposed layer 2. The layer 2 not masked with the layer 3 is altered by the implantation of the particles 4 to an insulating layer 5, and the layer 2 of the section masked with the layer 3 is altered to a first interconnection region 6. Then, after the layer 3 on the region 3 is removed, a conductive layer 7 made of a superconducting material is formed on the whole surface. Thereafter, the interconnection layer and the interlayer insulating film are sequentially formed similarly, to manufacture a semiconductor device having multilayer interconnection regions.
JP62245016A 1987-09-29 1987-09-29 Manufacture of semiconductor device Pending JPS6489342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245016A JPS6489342A (en) 1987-09-29 1987-09-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245016A JPS6489342A (en) 1987-09-29 1987-09-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6489342A true JPS6489342A (en) 1989-04-03

Family

ID=17127320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245016A Pending JPS6489342A (en) 1987-09-29 1987-09-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6489342A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354875A (en) * 1989-07-24 1991-03-08 Furukawa Electric Co Ltd:The Formation of superconductor circuit
JPH0355889A (en) * 1989-07-25 1991-03-11 Furukawa Electric Co Ltd:The Manufacture of superconducting multilayered circuit
JPH07263767A (en) * 1994-01-14 1995-10-13 Trw Inc Planar type high temperature superconducting integrated circuit using ion implantation.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354875A (en) * 1989-07-24 1991-03-08 Furukawa Electric Co Ltd:The Formation of superconductor circuit
JPH0355889A (en) * 1989-07-25 1991-03-11 Furukawa Electric Co Ltd:The Manufacture of superconducting multilayered circuit
JPH07263767A (en) * 1994-01-14 1995-10-13 Trw Inc Planar type high temperature superconducting integrated circuit using ion implantation.

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