KR910013528A - 전원 및 접지금속 배선의 설계방법 - Google Patents

전원 및 접지금속 배선의 설계방법 Download PDF

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Publication number
KR910013528A
KR910013528A KR1019890020114A KR890020114A KR910013528A KR 910013528 A KR910013528 A KR 910013528A KR 1019890020114 A KR1019890020114 A KR 1019890020114A KR 890020114 A KR890020114 A KR 890020114A KR 910013528 A KR910013528 A KR 910013528A
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KR
South Korea
Prior art keywords
metal wiring
power
design method
ground metal
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019890020114A
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English (en)
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KR920006187B1 (ko
Inventor
김대용
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020114A priority Critical patent/KR920006187B1/ko
Publication of KR910013528A publication Critical patent/KR910013528A/ko
Application granted granted Critical
Publication of KR920006187B1 publication Critical patent/KR920006187B1/ko
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음.

Description

전원 및 접지금속 배선의 설계방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 실시예.

Claims (1)

  1. 반도체 회로에 있어서, 전원전압 또는 접지선으로 사용되는 금속배선 상에 얇은 틈을 만들어 줌을 특징으로 하는 전원 접지금속 배선의 설계방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890020114A 1989-12-29 1989-12-29 전원 및 접지 금속 배선의 설계방법 Expired KR920006187B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020114A KR920006187B1 (ko) 1989-12-29 1989-12-29 전원 및 접지 금속 배선의 설계방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020114A KR920006187B1 (ko) 1989-12-29 1989-12-29 전원 및 접지 금속 배선의 설계방법

Publications (2)

Publication Number Publication Date
KR910013528A true KR910013528A (ko) 1991-08-08
KR920006187B1 KR920006187B1 (ko) 1992-08-01

Family

ID=19294153

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020114A Expired KR920006187B1 (ko) 1989-12-29 1989-12-29 전원 및 접지 금속 배선의 설계방법

Country Status (1)

Country Link
KR (1) KR920006187B1 (ko)

Also Published As

Publication number Publication date
KR920006187B1 (ko) 1992-08-01

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