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Priority to MYPI2014003297ApriorityCriticalpatent/MY171066A/en
Publication of MY171066ApublicationCriticalpatent/MY171066A/en
Synchronisation In Digital Transmission Systems
(AREA)
Abstract
[0030] There is disclosed a system for transferring data between two asynchronous clock domains, thus having at least a source clock (first clock domain) and a receiving clock (second clock domain); the system comprising: a multiplexer (20) for providing the first input; a register (30, 90) configured for receiving and storing data input at the first clock domain (1) and second clock domain (2); a comparison module (40,70) at the first clock domain (1) and second clock domains (2) configured for receiving incoming data input comparing data inputs; a controller (50, 80) at the first clock domain (1) and second clock domain (2) configured to receive the comparison output and toggling at least one signal (in2out) if a data change is detected based on the comparison; at least one synchronizer (60) to synchronizes signals into the second clock domain (2).
MYPI2014003297A2014-11-252014-11-25Method and system for transferring data through two different clock domains
MY171066A
(en)