NL7603732A - Vervaardiging van een halfgeleiderinrichting. - Google Patents

Vervaardiging van een halfgeleiderinrichting.

Info

Publication number
NL7603732A
NL7603732A NL7603732A NL7603732A NL7603732A NL 7603732 A NL7603732 A NL 7603732A NL 7603732 A NL7603732 A NL 7603732A NL 7603732 A NL7603732 A NL 7603732A NL 7603732 A NL7603732 A NL 7603732A
Authority
NL
Netherlands
Prior art keywords
semi
manufacture
conductor device
conductor
Prior art date
Application number
NL7603732A
Other languages
English (en)
Dutch (nl)
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of NL7603732A publication Critical patent/NL7603732A/xx

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302Non-deposition formation processes
    • H10P14/6304Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905Plural dram cells share common contact or common trench
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/911Differential oxidation and etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/945Special, e.g. metal
NL7603732A 1975-04-17 1976-04-08 Vervaardiging van een halfgeleiderinrichting. NL7603732A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50046698A JPS51121263A (en) 1975-04-17 1975-04-17 Method of manufacturing a semiconductor divice

Publications (1)

Publication Number Publication Date
NL7603732A true NL7603732A (nl) 1976-10-19

Family

ID=12754582

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7603732A NL7603732A (nl) 1975-04-17 1976-04-08 Vervaardiging van een halfgeleiderinrichting.

Country Status (7)

Country Link
US (1) US4114254A (fr)
JP (1) JPS51121263A (fr)
CA (1) CA1052476A (fr)
DE (1) DE2616857A1 (fr)
FR (1) FR2308199A1 (fr)
GB (1) GB1520051A (fr)
NL (1) NL7603732A (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2376513A1 (fr) * 1976-12-31 1978-07-28 Radiotechnique Compelec Dispositif semiconducteur muni d'un film protecteur
JPS5939906B2 (ja) * 1978-05-04 1984-09-27 超エル・エス・アイ技術研究組合 半導体装置の製造方法
CA1136773A (fr) * 1978-08-14 1982-11-30 Norikazu Ohuchi Dispositif semiconducteur
US4364078A (en) * 1978-08-15 1982-12-14 Synertek Edge barrier of polysilicon and metal for integrated circuit chips
US4242697A (en) * 1979-03-14 1980-12-30 Bell Telephone Laboratories, Incorporated Dielectrically isolated high voltage semiconductor devices
US5804485A (en) * 1997-02-25 1998-09-08 Miracle Technology Co Ltd High density metal gate MOS fabrication process
US5972804A (en) * 1997-08-05 1999-10-26 Motorola, Inc. Process for forming a semiconductor device
US5969382A (en) 1997-11-03 1999-10-19 Delco Electronics Corporation EPROM in high density CMOS having added substrate diffusion
US6068928A (en) * 1998-02-25 2000-05-30 Siemens Aktiengesellschaft Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
US7323422B2 (en) * 2002-03-05 2008-01-29 Asm International N.V. Dielectric layers and methods of forming the same
DE102007054484B3 (de) * 2007-11-15 2009-03-12 Deutsche Cell Gmbh Strukturier-Verfahren
US11171039B2 (en) * 2018-03-29 2021-11-09 Taiwan Semiconductor Manufacturing Company Ltd. Composite semiconductor substrate, semiconductor device and method for manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS541431B2 (fr) * 1973-12-26 1979-01-24

Also Published As

Publication number Publication date
GB1520051A (en) 1978-08-02
US4114254A (en) 1978-09-19
FR2308199B1 (fr) 1981-10-09
FR2308199A1 (fr) 1976-11-12
JPS51121263A (en) 1976-10-23
CA1052476A (fr) 1979-04-10
DE2616857A1 (de) 1976-10-28

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Legal Events

Date Code Title Description
BV The patent application has lapsed