TW200419908A - Mixed-voltage I/O design with novel floating n-well and gate-tracking circuits - Google Patents

Mixed-voltage I/O design with novel floating n-well and gate-tracking circuits

Info

Publication number
TW200419908A
TW200419908A TW092133936A TW92133936A TW200419908A TW 200419908 A TW200419908 A TW 200419908A TW 092133936 A TW092133936 A TW 092133936A TW 92133936 A TW92133936 A TW 92133936A TW 200419908 A TW200419908 A TW 200419908A
Authority
TW
Taiwan
Prior art keywords
buffer circuit
gate
voltage
transistor
mixed
Prior art date
Application number
TW092133936A
Other languages
English (en)
Other versions
TWI271927B (en
Inventor
Che-Hao Chuang
Ming-Dou Ker
Kuo-Chung Lee
Hsin-Chin Jiang
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Publication of TW200419908A publication Critical patent/TW200419908A/zh
Application granted granted Critical
Publication of TWI271927B publication Critical patent/TWI271927B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW092133936A 2003-03-28 2003-12-02 Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits TWI271927B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/400,873 US6838908B2 (en) 2003-03-28 2003-03-28 Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits

Publications (2)

Publication Number Publication Date
TW200419908A true TW200419908A (en) 2004-10-01
TWI271927B TWI271927B (en) 2007-01-21

Family

ID=32989303

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092133936A TWI271927B (en) 2003-03-28 2003-12-02 Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits

Country Status (2)

Country Link
US (1) US6838908B2 (zh)
TW (1) TWI271927B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW561608B (en) * 2002-11-01 2003-11-11 Silicon Integrated Sys Corp Electrostatic discharge protection apparatus for too-high or too-low input voltage reference level
US6965253B1 (en) * 2004-06-30 2005-11-15 Pericom Semiconductor Corp. Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching
TWI302025B (en) * 2006-05-25 2008-10-11 Univ Nat Chiao Tung Mixed-voltage input/output buffer having low-voltage design
US7375555B1 (en) * 2007-05-15 2008-05-20 Microchip Technology Incorporated Five volt tolerant integrated circuit signal pad with three volt assist
TW200926107A (en) * 2007-12-10 2009-06-16 Richtek Technology Corp A row driving cells of electroluminescent display and the method thereof
JP5282560B2 (ja) * 2008-12-19 2013-09-04 富士通セミコンダクター株式会社 半導体装置及びシステム
KR20100116253A (ko) * 2009-04-22 2010-11-01 삼성전자주식회사 입출력 회로 및 이를 포함하는 집적회로 장치
TWI508448B (zh) 2010-12-13 2015-11-11 Mstar Semiconductor Inc 低漏電之輸出入電路與相關裝置
US9484911B2 (en) 2015-02-25 2016-11-01 Qualcomm Incorporated Output driver with back-powering prevention
US20170358691A1 (en) * 2016-06-14 2017-12-14 Globalfoundries Inc. Reconfigurable MOS Varactor
US9792994B1 (en) * 2016-09-28 2017-10-17 Sandisk Technologies Llc Bulk modulation scheme to reduce I/O pin capacitance
KR102705446B1 (ko) * 2022-11-29 2024-09-11 에스케이키파운드리 주식회사 양방향 입출력 회로 및 이를 포함하는 집적 회로

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0836194B1 (en) * 1992-03-30 2000-05-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5864243A (en) 1996-09-18 1999-01-26 Vlsi Technology, Inc. Buffer and method for transferring data therein
US6014053A (en) * 1997-05-12 2000-01-11 Philips Electronics North America Corporation Amplifier MOS biasing circuit for a avoiding latch-up
JP3212915B2 (ja) * 1997-08-08 2001-09-25 ローム株式会社 半導体集積回路装置
US5959444A (en) * 1997-12-12 1999-09-28 Micron Technology, Inc. MOS transistor circuit and method for biasing a voltage generator
JP2001156619A (ja) * 1999-11-25 2001-06-08 Texas Instr Japan Ltd 半導体回路
JP2002116237A (ja) * 2000-10-10 2002-04-19 Texas Instr Japan Ltd 半導体集積回路
US6510088B2 (en) * 2001-03-22 2003-01-21 Winbond Electronics Corporation Semiconductor device having reduced leakage and method of operating the same
TW473979B (en) * 2001-03-28 2002-01-21 Silicon Integrated Sys Corp ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique
US6747501B2 (en) * 2001-07-13 2004-06-08 Industrial Technology Research Institute Dual-triggered electrostatic discharge protection circuit
TW529153B (en) * 2002-02-27 2003-04-21 United Microelectronics Corp Electrostatic discharge protection circuit

Also Published As

Publication number Publication date
US20040189345A1 (en) 2004-09-30
US6838908B2 (en) 2005-01-04
TWI271927B (en) 2007-01-21

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Legal Events

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