TW200611331A - Method of forming improved rounded corners in sti features - Google Patents

Method of forming improved rounded corners in sti features

Info

Publication number
TW200611331A
TW200611331A TW094114020A TW94114020A TW200611331A TW 200611331 A TW200611331 A TW 200611331A TW 094114020 A TW094114020 A TW 094114020A TW 94114020 A TW94114020 A TW 94114020A TW 200611331 A TW200611331 A TW 200611331A
Authority
TW
Taiwan
Prior art keywords
sti
opening
etching
semiconductor substrate
rounded corners
Prior art date
Application number
TW094114020A
Other languages
English (en)
Other versions
TWI293483B (en
Inventor
Po-Jen Chen
Jen-Hsiang Leu
Yan-Chang Liu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200611331A publication Critical patent/TW200611331A/zh
Application granted granted Critical
Publication of TWI293483B publication Critical patent/TWI293483B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
TW094114020A 2004-09-23 2005-04-29 Method of forming improved rounded corners in sti features TWI293483B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/948,934 US7148120B2 (en) 2004-09-23 2004-09-23 Method of forming improved rounded corners in STI features

Publications (2)

Publication Number Publication Date
TW200611331A true TW200611331A (en) 2006-04-01
TWI293483B TWI293483B (en) 2008-02-11

Family

ID=36074601

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094114020A TWI293483B (en) 2004-09-23 2005-04-29 Method of forming improved rounded corners in sti features

Country Status (2)

Country Link
US (1) US7148120B2 (zh)
TW (1) TWI293483B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4961668B2 (ja) * 2005-01-11 2012-06-27 富士電機株式会社 半導体装置の製造方法
KR101232137B1 (ko) * 2005-11-21 2013-02-12 엘지디스플레이 주식회사 인쇄판, 인쇄판의 제조방법 및 그를 이용한 액정표시소자제조방법
US20080050871A1 (en) * 2006-08-25 2008-02-28 Stocks Richard L Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures
US20090230438A1 (en) * 2008-03-13 2009-09-17 International Business Machines Corporation Selective nitridation of trench isolation sidewall
JP2010135624A (ja) * 2008-12-05 2010-06-17 Tokyo Electron Ltd 半導体装置の製造方法
CN101996877B (zh) * 2009-08-14 2012-07-04 中芯国际集成电路制造(上海)有限公司 刻蚀方法以及形成浅沟槽隔离结构的方法
US8835994B2 (en) 2010-06-01 2014-09-16 International Business Machines Corporation Reduced corner leakage in SOI structure and method
CN104183533A (zh) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 一种制作半导体器件的方法
DE102014115253A1 (de) * 2014-10-20 2016-04-21 Osram Opto Semiconductors Gmbh Verfahren zur Strukturierung einer Schichtenfolge und Halbleiterlaser-Vorrichtung
US9847425B2 (en) * 2016-03-24 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with a semiconductor strip as a base
CN110660654B (zh) * 2019-09-30 2022-05-03 闽南师范大学 一种超高质量SOI基键合Ge薄膜的制备方法
GB201917734D0 (en) * 2019-12-04 2020-01-15 Spts Technologies Ltd Method, substrate and apparatus
US11877434B2 (en) * 2020-07-09 2024-01-16 Micron Technology, Inc. Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems
CN114864477B (zh) * 2021-01-20 2024-09-20 长鑫存储技术有限公司 半导体结构及其制造方法
CN115206870B (zh) * 2021-04-13 2026-03-10 中国科学院微电子研究所 一种浅沟槽隔离区域和dram及其制造方法
US12185526B2 (en) 2021-08-02 2024-12-31 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory
CN113766412B (zh) * 2021-11-05 2022-02-15 绍兴中芯集成电路制造股份有限公司 具有弧形底角的凹槽的制备方法、mems麦克风的制备方法
CN115547825B (zh) * 2022-09-29 2026-03-24 北京北方华创微电子装备有限公司 衬底沟槽刻蚀方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5807789A (en) * 1997-03-20 1998-09-15 Taiwan Semiconductor Manufacturing, Co., Ltd. Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI)
US6258676B1 (en) * 1999-11-01 2001-07-10 Chartered Semiconductor Manufacturing Ltd. Method for forming a shallow trench isolation using HDP silicon oxynitride
KR100428806B1 (ko) * 2001-07-03 2004-04-28 삼성전자주식회사 트렌치 소자분리 구조체 및 그 형성 방법
US6500727B1 (en) * 2001-09-21 2002-12-31 Taiwan Semiconductor Manufacturing Company Silicon shallow trench etching with round top corner by photoresist-free process
US6548399B1 (en) * 2001-11-20 2003-04-15 Intel Corporation Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer
KR100480897B1 (ko) * 2002-12-09 2005-04-07 매그나칩 반도체 유한회사 반도체소자의 소자분리막 형성방법
JP4825402B2 (ja) * 2004-01-14 2011-11-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US7148120B2 (en) 2006-12-12
US20060063348A1 (en) 2006-03-23
TWI293483B (en) 2008-02-11

Similar Documents

Publication Publication Date Title
TW200611331A (en) Method of forming improved rounded corners in sti features
US9190313B2 (en) Shallow trench isolation structures
TW200614418A (en) Semiconductor device having dual-sti (shallow trench isolation) and manufacturing method thereof
US8492838B2 (en) Isolation structures for SOI devices with ultrathin SOI and ultrathin box
CN103681452B (zh) 沟渠绝缘工艺
US20090191688A1 (en) Shallow Trench Isolation Process Using Two Liners
EP1164636A3 (en) Method to form self aligned, L-shaped sidewall spacers
TWI266368B (en) Method of forming an STI feature to avoid electrical charge leakage
US8629514B2 (en) Methods and structures for customized STI structures in semiconductor devices
TW200601486A (en) Method for forming device isolation film of semiconductor device
KR100590383B1 (ko) 반도체 소자의 소자분리막 형성방법
US9337259B2 (en) Structure and method to improve ETSOI MOSFETS with back gate
EP1353369A3 (en) Method for producing semiconductor device
TW200518223A (en) Method for forming openings in insulation layer and stacked insulation layer above conductive region and semiconductor substrate
CN103066007B (zh) 一种全隔离结构的制作方法
WO2005071738A3 (en) Shallow trench isolation process and structure
WO2006118673A3 (en) Method of forming shallow trench isolation structures in the logic and memory areas
CN104347507A (zh) 半导体器件的形成方法
US6998324B2 (en) Methods of fabricating silicon on insulator substrates for use in semiconductor devices
JP2007519217A5 (zh)
CN1316587C (zh) 结绝缘有源组件的形成方法
TWI702687B (zh) 未平面化的淺溝槽隔離形成
CN101238558B (zh) 制造双极晶体管的方法
KR100700282B1 (ko) 반도체 소자의 제조 방법
KR20100008966A (ko) 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees