TW200614031A - Constraints-directed compilation for heterogeneous reconfigurable architectures - Google Patents

Constraints-directed compilation for heterogeneous reconfigurable architectures

Info

Publication number
TW200614031A
TW200614031A TW094109582A TW94109582A TW200614031A TW 200614031 A TW200614031 A TW 200614031A TW 094109582 A TW094109582 A TW 094109582A TW 94109582 A TW94109582 A TW 94109582A TW 200614031 A TW200614031 A TW 200614031A
Authority
TW
Taiwan
Prior art keywords
constraints
heterogeneous reconfigurable
compilation
reconfigurable architectures
directed
Prior art date
Application number
TW094109582A
Other languages
English (en)
Other versions
TWI310144B (en
Inventor
Vicki Tsai
Hooman Honary
Ernest Tsui
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200614031A publication Critical patent/TW200614031A/zh
Application granted granted Critical
Publication of TWI310144B publication Critical patent/TWI310144B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/10—Processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
TW094109582A 2004-03-31 2005-03-28 Constraints-directed compilation for heterogeneous reconfigurable architectures TWI310144B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/814,568 US7073159B2 (en) 2004-03-31 2004-03-31 Constraints-directed compilation for heterogeneous reconfigurable architectures

Publications (2)

Publication Number Publication Date
TW200614031A true TW200614031A (en) 2006-05-01
TWI310144B TWI310144B (en) 2009-05-21

Family

ID=34978644

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094109582A TWI310144B (en) 2004-03-31 2005-03-28 Constraints-directed compilation for heterogeneous reconfigurable architectures

Country Status (6)

Country Link
US (1) US7073159B2 (zh)
JP (1) JP2007527075A (zh)
KR (1) KR100856803B1 (zh)
MY (1) MY143029A (zh)
TW (1) TWI310144B (zh)
WO (1) WO2005098649A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8751722B2 (en) 2008-05-30 2014-06-10 Intel Corporation Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050149890A1 (en) * 2003-12-29 2005-07-07 Tsai Vicki W. Programming reconfigurable packetized networks
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US20050223110A1 (en) * 2004-03-30 2005-10-06 Intel Corporation Heterogeneous building block scalability
US20050229139A1 (en) * 2004-03-30 2005-10-13 Intel Corporation Block-based processing in a packet-based reconfigurable architecture
US7073159B2 (en) 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures
US7257757B2 (en) * 2004-03-31 2007-08-14 Intel Corporation Flexible accelerators for physical layer processing
US20060004902A1 (en) * 2004-06-30 2006-01-05 Siva Simanapalli Reconfigurable circuit with programmable split adder
US7568059B2 (en) 2004-07-08 2009-07-28 Asocs Ltd. Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
US20090327546A1 (en) * 2005-03-03 2009-12-31 Gaby Guri System for and method of hand-off between different communication standards
JP4647533B2 (ja) * 2005-11-28 2011-03-09 富士通セミコンダクター株式会社 演算処理装置、演算処理装置の内部構成決定方法および演算処理システム
US7673272B1 (en) * 2007-02-16 2010-03-02 Xilinx, Inc. Method and apparatus for generating an area constraint for a module in a programmable logic device
KR101358371B1 (ko) * 2007-09-14 2014-02-04 삼성전자주식회사 전력 시뮬레이션 방법 및 전력 시뮬레이터
KR101053903B1 (ko) * 2007-10-19 2011-08-04 삼성전자주식회사 네트워크온칩에서 전압 및 주파수 제어 장치 및 방법
JP5163332B2 (ja) * 2008-07-15 2013-03-13 富士通セミコンダクター株式会社 設計プログラム、設計装置、および設計方法
WO2010029812A1 (ja) * 2008-09-09 2010-03-18 日本電気株式会社 マルチコアにおけるプログラミングシステム、その方法及びそのプログラム
US8656375B2 (en) * 2009-11-02 2014-02-18 International Business Machines Corporation Cross-logical entity accelerators
US8201126B1 (en) * 2009-11-12 2012-06-12 Altera Corporation Method and apparatus for performing hardware assisted placement
US20120185820A1 (en) * 2011-01-19 2012-07-19 Suresh Kadiyala Tool generator
US8789026B2 (en) 2011-08-02 2014-07-22 International Business Machines Corporation Technique for compiling and running high-level programs on heterogeneous computers
US8667444B2 (en) * 2012-02-17 2014-03-04 Synopsys, Inc. Concurrent placement and routing using hierarchical constraints
US8850413B2 (en) * 2012-05-31 2014-09-30 Oracle International Corporation Compiling multi-threaded applications for targeted criticalities
CN116610455B (zh) * 2023-07-18 2023-12-05 之江实验室 一种可编程网元设备的资源约束描述系统及方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US6205579B1 (en) * 1996-10-28 2001-03-20 Altera Corporation Method for providing remote software technical support
US6112023A (en) * 1997-02-24 2000-08-29 Lucent Technologies Inc. Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems
US6038386A (en) * 1997-08-21 2000-03-14 Xilinx, Inc. Method for controlling power and slew in a programmable logic device
US6195788B1 (en) * 1997-10-17 2001-02-27 Altera Corporation Mapping heterogeneous logic elements in a programmable logic device
GB9828381D0 (en) 1998-12-22 1999-02-17 Isis Innovation Hardware/software codesign system
US6941538B2 (en) * 2002-02-22 2005-09-06 Xilinx, Inc. Method and system for integrating cores in FPGA-based system-on-chip (SoC)
US7000211B2 (en) * 2003-03-31 2006-02-14 Stretch, Inc. System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources
US20050149890A1 (en) * 2003-12-29 2005-07-07 Tsai Vicki W. Programming reconfigurable packetized networks
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US20050223110A1 (en) * 2004-03-30 2005-10-06 Intel Corporation Heterogeneous building block scalability
US20050229139A1 (en) * 2004-03-30 2005-10-13 Intel Corporation Block-based processing in a packet-based reconfigurable architecture
US7073159B2 (en) 2004-03-31 2006-07-04 Intel Corporation Constraints-directed compilation for heterogeneous reconfigurable architectures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8751722B2 (en) 2008-05-30 2014-06-10 Intel Corporation Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
TWI452470B (zh) * 2008-05-30 2014-09-11 Intel Corp 用於配合異質資源使用的設備、系統和方法
US9547618B2 (en) 2008-05-30 2017-01-17 Intel Corporation Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)

Also Published As

Publication number Publication date
US7073159B2 (en) 2006-07-04
MY143029A (en) 2011-02-14
US20050229140A1 (en) 2005-10-13
KR100856803B1 (ko) 2008-09-05
WO2005098649A2 (en) 2005-10-20
WO2005098649A3 (en) 2005-11-24
TWI310144B (en) 2009-05-21
KR20060130694A (ko) 2006-12-19
JP2007527075A (ja) 2007-09-20

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees