201110836 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種電路板及其製作方法，特別是·於一種内 埋式元件基板結構及其製作方法。 【先前技術】 近年來’ ik著電子技術的日新月異，更人性化、功能更佳的電子 產品不斷地推陳出新，並朝向輕、薄、短、小的趨勢設計。在這些 電子產品内通常會配置電路板，用以承載單個晶片或多個晶片，以 作為電子產品的資料處理單元，然而晶片配置於電路板表面上會造 成承載面積增加，因而將晶片或元件内嵌於電路基板中的内埋式元 件基板’已成為當前的技術趨勢。 第1圖繪示的是習知内埋式元件基板的剖面示意圖。如第1圖所 示’習知内埋式元件基板400主要由核心板410、外層線路板420 及外層線路板430壓合而成，在核心板410中設有一開孔41〇a用來 容置一内埋式元件500，其中，内埋式元件500係以錫膏表面貼裝 (SMT)上件，也就是說，在外層線路板430上必須預作面積較大的 SMT銅墊432，並且必須確保錫膏440不會溢流’例如預作阻錫膏 流動之溝槽或其它結構。 201110836 此外’習知随式元件基板的導軌_通常為充填銀顆粒 與樹脂複合材料所組成的轉，由於僅姻細小銀顆粒之間的物理 接觸作為雜料，故其科通性較差，加上導軌與峨的介面 無金屬結合，造成習知内埋式元件基板的信賴性較差。 由此可知，該領域目前仍需要—種改㈣内埋式元件基板結構及 其製程方法，以解決上述習知技藝之不足與缺點。 【發明内容】 本發明之主要目的在提供—種改良之岐式元件基板結構 製作方法。 ' 本發明-較佳實施例提供一種内埋式元件基板結構的製作方 法。首先提供-核心電路板，包含有—開孔及複數個連接銅塾，其 上設有複數個第-導電凸塊；提供—她，包含—基材及—表面鋼 層’其上設有複數個第二導電凸塊，以及—内埋式元件置於導電 凸塊上並與其接合；提供—巾間接合材，在相對應於該核心電路板 的該開孔處，設有—貫穿孔；以及進行-壓合製程，職核心電路 板、該中間接合材及該她壓合在ϋ該第_導電凸塊穿過該 中間接合材而與該表面銅層電連接，並形成一合金介面。 201110836 本發明另-較佳實施例提供埋式元件基板結構，包含有一 核心電路板，其包含有一開孔及複數個連接銅墊；一内埋式元件 置於該開⑽；以及複數個合錄塞，相設於該複數個^銅塾 上，並與-外層線路電連接，且各該合金插塞與該外層 有一合金介面。 间八 為讓本發明之上述目的、特徵、和優點能更鶴紐，下文特兴 籲較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之車: =實施方式期式僅供參考與說日，麟用來縣發明加以限制 者0 【實施方式】 …目第2圖至第9圖’其為依據本發曝佳實施例所綠示的内 中僅=Γ+Γ_方法示4圖。_的是，_至第9圖 」四層線職為卿範·，但本發明不限於此種 二说路板結構’熟習該項技藝者應能理解本發明也可以被應用於 核心板、連結缺私多結構或者其製程。 首先’如第2圖所干^ 4 例如，絕緣材，^ 核心電路板1，包括-批基板10， 面lb， /、中，核心基板10包含有一上表面la以及一下表 圖案lOa^T基板1〇的上表面13及下表面lb已分別形成導線 、 例如，導線圖案1〇3至少可以包括連接銅墊12a 201110836 以及細線路14a，導線圖案l〇b至少可以包括連接銅墊i2b以及細 線路14b。 此外’在核心基板10中已形成有複數個連通上表面1&及下表面 lb的導線圖案i〇a及10b的導電通孔結構16，例如，導電通孔結構 16電連接形成在核心基板1〇上表面la的連接銅墊12&以及形成在 核心基板10下表面lb的連接銅塾12b。 舉例來說，形成上述的核心電路板丨的步驟可以包括有：（1)提 i、核〜層薄板或一銅笛基板；(2)進行機械或雷射鑽通孔製程；(3) 銅電鍍通孔；及(4)線路蝕刻。 如第3圖所示，在核心電路板！的預定位置進行開孔製程,例如， 以雷射或者機械成型機具’在核心電路板丨的預定位置形成一貫穿 核心基板ίο上表面la及下表面lb的航18。關錢係用來在 後續步驟中容置一内埋式元件。 ία civ -5 如第4A圖所示’接著，至少在核心電路板i的上表面“ 接銅墊以上，利用印刷方式形成錐形的導電凸塊ιΐ2，直中， ^幻12可以是銅|錫(Cu職n)、銅仙錫(物驗 銅-鉍-鋅-錫等銅膏( 甚至低於20(TC以下。 胁點應低於210 ( 201110836 m 根據本發明之較佳實施例，導電凸塊112較佳為銅_鉍_錫 (Cu/Bi/Sn)配方銅合金膠，其熔點為19〇。(：左右。在印刷步驟之後， 接著進行一烘烤製程，在作業溫度約90-12(TC的環境下，使導電凸 塊112硬化。 如第4B圖所示，另外提供一載板2，其包含一基材2〇以及一表 面銅層22。例如，載板2可以是一可撕離銅箔，或是金屬載板上電 鍍12/mi銅層。同樣的，利用印刷方式，在載板2的表面銅層22上 的預疋位置形成錐形的導電凸塊212，其中，導電凸塊212可以是 銅-叙-錫(Cu/Bi/Sn)、銅-銀錫(Cu/Ag/Bi/Sn)、銅-纽-鋅-錫 (Cu/Bi/Zn/Sn)等銅膏或銅合金膠，其熔點應低於21〇。〇，甚至低於 200°C以下。 根據本發明之較佳實施例，導電凸塊212較佳為銅鉍錫 (Cu/Bi/Sn)配方銅膏或銅合金膠所構成者，其熔點較佳為丨卯它左 •右。在印刷步驟之後，接著進行一烘烤製程，在作業溫度約90-120Ϊ 下，使導電凸塊212硬化。 如第4C圖所示，另外提供一載板3，其包含一基材％以及一表 面銅層32。例如’載板3可以是一可撕離銅落，或是金屬載板上電 鍍12/"m銅層。同樣的，利用印刷方式在載板3的表面銅層32上的 預定位置形成導電凸塊m，其中，導電凸塊犯可以是銅备錫 (Cu/Bi/Sn)鋼-銀_鉍_錫(Cu/Ag/Bi/Sn)、銅备辞錫(以腕21^)等 201110836 銅膏或銅合金膠，制:點應低於21Gt,甚至低於·。c以下。 根據本發明之較佳實施例，導電凸塊312較佳為銅善錫 (Cu/Bi/Sn)配方銅合娜，其魅為·t左右。在印刷步驟之後， 接著將-内埋式元件3〇〇置於導電凸塊312上並與其接合。隨後進 行-烘烤製程’在作業溫度約9(Μ2()ΐτ，使導電凸塊312硬化。 前述的内埋式元件300可以是半導體積體電路晶片或被動元件等 等。 如第4D圖所示，另外提供一中間接合材4，例如，片狀膠片 (Prepreg)、FR5 或 ABF(Ajinomotobuild-up film)介電層膜等材質， 在相對應於核心電路板1的開孔18的預定位置上，形成一預設貫穿 孔 48。 ' 如第5A圖及第5B圖所示，接著將第4A圖所示的核心電路板 1、第4B圖所示的載板2及第4C圖所示的載板3在一低壓下以及 相對低溫下層疊並壓合在一起，其中，核心電路板丨被夾在載板2 與载板3之間，核心電路板丨與載板3之間是第4〇圖所示的中間 接合材4 ’其預設貫穿孔48相對應於核心電路板丨的開孔18，用來 容置内埋式元件300 ’核心電路板1與載板2之間則是另一中間接 合材5。 根據本發明之較佳實施例’前述的低壓約為〇.5Mpa〜3Mpa，而 201110836 .範圍 别述的相對低溫約為祕綱。c，例如，19(rc左右。前 Ά圍係用來使巾間接合材4及中間接合材5固化的溫度 ' 在進行前述的壓合製程時，核心電路板1上的導電凸塊112會 穿過中間接合材4 ’直接與觀3絲賴層32電連接，並且在前 述的相對低溫環境下’導電凸塊⑴會純板3的麵崎％反應 形成合金介面6G，例如，銅善錫(Cu/Bi/Sn)合金，形成良好的電^ 接觸’而導電凸塊U2本身也會轉變成合金插塞U2a。 同樣的，载板2上的導電凸塊212會穿過中間接合材5，與核心 電路板1上的連接銅墊12b電連接’並且在前述的相對低溫環境 導電凸塊212會與連接銅塾12b反應形成合金介面，例如，銅^ 錫(Cu/Bi/Sn)合金’形成良好的電性接觸，而導電凸塊212本身也會 轉變成合金插塞212a。此外，在前述的壓合過程中，載板3上的導 電凸塊312也會轉變成合金凸塊312a，與内埋式元件3〇〇之間形成 Φ 良好的電性接觸。 如第6圖所示，接著進行载板剝離製程，利用钱刻或手動方式， 分別將載板2的基材2G及載板3的基材3G剝除，僅留下表面銅層 22 及 32。 θ 如第7圖所示’在剝除載板2的基材2〇及載板3的基材3〇之後， 隨後進行-外躲雜㈣程，絲面編22及32分韻刻成所 11 201110836 要的電路圖案220及320,其中，電路圖案22〇至少包括銅墊222 及細線路224，電路圖案320至少包括銅墊322、332及細線路324。 根據本發明之較佳實施例，銅墊222與核心電路板i上的連接銅墊 12b之間為合金插塞212a，銅墊322與核心電路板丨上的連接銅墊 12a之間為合金插塞112a，銅墊332與内埋式元件3〇〇之間為合金 凸塊312a。 如第8圖所示，在完成外層線路敍刻製程之後，接著分別在電路 圖案220及320上覆蓋-防焊阻劑層7〇以及一防焊阻劑層8〇，並· 在防焊阻劑層70形成防焊開孔7〇a，在防焊阻劑層80形成防焊開 孔80a，使其分別曝露出部分的銅墊322及銅塾222。 如第9圖所示’在形成防焊阻劑層7〇、8〇及防焊開孔施、術201110836 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of fabricating the same, and more particularly to an embedded component substrate structure and a method of fabricating the same. [Prior Art] In recent years, ik has been evolving with electronic technology, and more humanized and functional electronic products have been continuously introduced, and are designed to be light, thin, short, and small. In these electronic products, a circuit board is usually arranged to carry a single wafer or a plurality of wafers as a data processing unit of an electronic product. However, when the wafer is disposed on the surface of the circuit board, the bearing area is increased, and thus the wafer or the component is inside. The embedded component substrate embedded in the circuit substrate has become a current technology trend. FIG. 1 is a schematic cross-sectional view showing a conventional embedded device substrate. As shown in FIG. 1 , the conventional buried component substrate 400 is mainly formed by pressing the core board 410 , the outer layer board 420 and the outer layer board 430 . The core board 410 is provided with an opening 41 〇 a for accommodating An embedded component 500, wherein the embedded component 500 is soldered with a surface mount (SMT) upper member, that is, an SMT copper pad 432 having a larger area must be pre-made on the outer circuit board 430, and It must be ensured that the solder paste 440 does not overflow, such as trenches or other structures pre-emptive solder paste flow. 201110836 In addition, the guide rail of the conventional component substrate _ is usually composed of a silver-filled particle and a resin composite material. Since only the physical contact between the fine silver particles is used as a miscellaneous material, the scientific compatibility is poor. The rail and the interface of the crucible are not metal-bonded, resulting in poor reliability of the conventional embedded component substrate. It can be seen that there is still a need in the art for a modified (4) embedded component substrate structure and a method of fabricating the same to solve the above-mentioned deficiencies and shortcomings of the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide an improved method for fabricating a substrate structure of a germanium element. The present invention - a preferred embodiment provides a method of fabricating a buried component substrate structure. Firstly, a core circuit board is provided, comprising: an opening and a plurality of connecting copper cymbals, wherein a plurality of first conductive bumps are arranged thereon; and the -including, the substrate and the surface steel layer are provided thereon a second conductive bump, and the embedded component is placed on and engaged with the conductive bump; and an inter-shield joint material is provided, and a through hole is provided at the opening corresponding to the core circuit board; And performing a press-bonding process, the core circuit board, the intermediate bonding material, and the press-bonding of the first conductive bump through the intermediate bonding material to electrically connect the surface copper layer and form an alloy interface. 201110836 Another preferred embodiment of the present invention provides a buried component substrate structure including a core circuit board including an opening and a plurality of connecting copper pads; a buried component disposed in the opening (10); and a plurality of recordings The plug is disposed on the plurality of copper mats and electrically connected to the outer layer, and each of the alloy plugs has an alloy interface with the outer layer. The above described objects, features, and advantages of the present invention will become more apparent from the following description. However, the following vehicles: = The implementation period is for reference and only for the day, and the Lin is used by the county invention to limit it. [Embodiment] ... Figure 2 to Figure 9 is based on the preferred embodiment of the present invention. In the middle of the green display, only = Γ + Γ _ method shows 4 map. _ _ _ to _ 9 ” four-line line is Qing Fan, but the invention is not limited to this two-way road structure. Those skilled in the art should understand that the invention can also be applied to the core board, Linking multiple structures or their processes. First, as shown in FIG. 2, for example, an insulating material, a core circuit board 1, including a batch substrate 10, a surface lb, /, a core substrate 10 including an upper surface 1a and a lower surface pattern lOa^T substrate The upper surface 13 and the lower surface 1b of the 1〇 have respectively formed the wires. For example, the wire pattern 1〇3 may include at least the connection copper pad 12a 201110836 and the thin line 14a, and the wire pattern l〇b may at least include the connection copper pad i2b and the fine line 14b. Further, a plurality of conductive via structures 16 that connect the conductor patterns i 〇 a and 10 b of the upper surface 1 & and the lower surface lb have been formed in the core substrate 10 . For example, the conductive via structures 16 are electrically connected to each other on the core substrate 1 . The connection copper pad 12& of the upper surface la and the connection copper pad 12b formed on the lower surface lb of the core substrate 10. For example, the steps of forming the core circuit board described above may include: (1) mentioning i, core ~ layer sheet or a copper flute substrate; (2) performing mechanical or laser drilling through hole manufacturing; (3) copper Plated through holes; and (4) line etching. As shown in Figure 3, on the core board! The predetermined position is subjected to an opening process, for example, by a laser or mechanical forming tool 'forming a predetermined position of the core circuit board 一 a hang 18 penetrating the upper surface la and the lower surface lb of the core substrate ί. The money is used to house a buried component in a subsequent step. Ία civ -5 as shown in Fig. 4A 'Next, at least on the upper surface of the core circuit board i' above the copper pad, using the printing method to form a tapered conductive bump ι 2, straight, ^ illusion 12 can be copper | Tin (Cu job n), copper tin (physical test copper-bismuth-zinc-tin and other copper paste (even below 20 (TC below. The threat point should be lower than 210 (201110836 m according to a preferred embodiment of the present invention, The conductive bump 112 is preferably a copper-bismuth (Cu/Bi/Sn) formula copper alloy paste having a melting point of 19 Å. (: about right and left. After the printing step, a baking process is followed, at an operating temperature of about In the environment of 90-12, the conductive bumps 112 are hardened. As shown in FIG. 4B, a carrier 2 is further provided, which comprises a substrate 2〇 and a surface copper layer 22. For example, the carrier 2 can It is a peelable copper foil or a 12/mi copper layer plated on a metal carrier. Similarly, a tapered conductive bump 212 is formed on the surface copper layer 22 of the carrier 2 by a printing method. The conductive bump 212 may be copper-sodium-tin (Cu/Bi/Sn), copper-silver-tin (Cu/Ag/Bi/Sn), copper-new-zinc-tin (Cu/Bi/Zn/ Sn) or other copper paste or copper alloy glue, which melts The point should be less than 21 〇. 〇, even below 200 ° C. According to a preferred embodiment of the invention, the conductive bump 212 is preferably a copper bismuth (Cu / Bi / Sn) formula copper paste or copper alloy glue The constituents have a melting point of preferably left and right. After the printing step, a baking process is then performed to harden the conductive bumps 212 at an operating temperature of about 90-120 Torr. As shown in Fig. 4C Further, a carrier 3 is provided, which comprises a substrate % and a surface copper layer 32. For example, the carrier 3 may be a peelable copper drop or a 12/<m copper layer on a metal carrier. Similarly, a conductive bump m is formed on a predetermined position on the surface copper layer 32 of the carrier 3 by a printing method, wherein the conductive bump may be a copper-prepared tin (Cu/Bi/Sn) steel-silver_铋_tin. (Cu/Ag/Bi/Sn), copper preparation tin (to wrist 21^), etc. 201110836 copper paste or copper alloy glue, the system: the point should be lower than 21Gt, or even lower than · c. According to the present invention In a preferred embodiment, the conductive bump 312 is preferably a copper/tin (Cu/Bi/Sn) formulation of copper, which has a charm of about t. After the printing step, the buried component is then placed. Conductive And bonding to the block 312. Subsequently, the baking process is performed at a working temperature of about 9 (Μ2() ΐτ to harden the conductive bumps 312. The aforementioned buried component 300 may be a semiconductor integrated circuit chip or a passive component. As shown in FIG. 4D, an intermediate bonding material 4, for example, a prepreg, FR5 or ABF (Ajinomoto build-up film) dielectric film, is provided, corresponding to the core circuit board 1 A predetermined through hole 48 is formed at a predetermined position of the opening 18. ' As shown in Figs. 5A and 5B, the core board 1 shown in Fig. 4A, the carrier 2 shown in Fig. 4B, and the carrier 3 shown in Fig. 4C are then under a low pressure and relative Laminated and pressed together at a low temperature, wherein the core circuit board 夹 is sandwiched between the carrier board 2 and the carrier board 3, and between the core circuit board 丨 and the carrier board 3 is the intermediate bonding material 4 shown in FIG. 'The predetermined through hole 48 corresponds to the opening 18 of the core circuit board ,, and is used to accommodate the embedded component 300. Between the core circuit board 1 and the carrier 2 is another intermediate bonding material 5. According to a preferred embodiment of the present invention, the aforementioned low pressure is about M5 Mpa to 3 MPa, and the relative low temperature of the range of 201110836 is about a secret. c, for example, 19 (about rc. The front lining is used to cure the temperature of the inter-sheet joint material 4 and the intermediate joint material 5). When performing the aforementioned nip process, the conductive bumps 112 on the core circuit board 1 will Through the intermediate bonding material 4' is directly connected to the viewing 3 wire layer 32, and in the aforementioned relatively low temperature environment, the conductive bump (1) will react with the surface of the pure plate 3 to form an alloy interface 6G, for example, copper good tin The (Cu/Bi/Sn) alloy forms a good electrical contact' and the conductive bump U2 itself is also transformed into the alloy plug U2a. Similarly, the conductive bumps 212 on the carrier 2 pass through the intermediate bonding material 5 , electrically connected to the connection copper pad 12b on the core circuit board 1 and in the aforementioned relatively low temperature environment, the conductive bump 212 reacts with the connection copper bead 12b to form an alloy interface, for example, a copper/tin (Cu/Bi/Sn) alloy. 'The formation of good electrical contact, and the conductive bump 212 itself will also be converted into the alloy plug 212a. In addition, during the aforementioned pressing process, the conductive bump 312 on the carrier 3 will also be transformed into the alloy bump 312a. , forming a good electrical contact with the buried component 3〇〇. As shown in Fig. 6. Next, the carrier peeling process is carried out, and the substrate 2G of the carrier 2 and the substrate 3G of the carrier 3 are peeled off by the money or manual method, leaving only the surface copper layers 22 and 32. θ as the seventh As shown in the figure, after the substrate 2 of the carrier 2 and the substrate 3 of the carrier 3 are stripped, the process is followed by the outer (four) process, and the 22 and 32 points of the silk are engraved into the 11 201110836. The circuit patterns 220 and 320, wherein the circuit pattern 22A includes at least a copper pad 222 and a thin line 224. The circuit pattern 320 includes at least copper pads 322, 332 and thin lines 324. According to a preferred embodiment of the present invention, the copper pads 222 and An alloy plug 212a is connected between the connection copper pads 12b on the core circuit board i, and an alloy plug 112a, a copper pad 332 and a buried component 3 are interposed between the copper pad 322 and the connection copper pad 12a on the core circuit board. Between the turns is an alloy bump 312a. As shown in Fig. 8, after the outer layer wiring process is completed, the circuit patterns 220 and 320 are respectively covered with a solder resist layer 7 and a solder resist layer. 8〇, and a solder resist opening 7a is formed in the solder resist layer 70, and a solder resist opening 80a is formed in the solder resist layer 80. Sook copper pad 322 and expose the copper portion 222. As shown in FIG. 9 'is formed in the resist layer 7〇 solder resist, and solder resist opening 8〇 administration, intraoperative
之後’接著，進行後段錫球加工及表面處理步驟，在防焊開孔I 曝路出的銅塾322上形成錫球72，而在開孔.曝露出的銅塾 上形成保護層82，例如，化鎳金、有機保焊劑(〇职心邊灿卿籲 preservative，OSP)等。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所 做之均等變化與修飾，皆闕本發明之涵蓋範圍。 【圖式簡單說明】 12 201110836 第1圖緣示的是習知内埋式树絲賴面示意圖。 第9圖為依據本發明較佳實施例所繪示的内埋式元件基板 結構製作方法示意圖。 【主要元件符號說明】 1核心電路板 lb下表面 l〇a導線圖案 12a連接銅塾 14a細線路 16導電通孔結構 112導電凸塊 2載板 20基材 212導電凸塊 220電路圖案 224細線路 3載板 30基材 300内埋式元件 312a合金凸塊 322銅塾 la上表面 10核心基板 l〇b導線圖案 12b連接銅墊 14b細線路 18開孔 112a合金插塞 22表面鋼層 212a合金插塞 222銅塾 32表面鋼層 312導電凸塊 320電路圖案 324細線路 13 201110836 332銅墊 4中間接合材 48貫穿孔 5中間接合材 60合金介面 70防焊阻劑層 70a防焊開孔 72錫球 80防焊阻劑層 80a防焊開孔 82保護層 • 400内埋式元件基板 C 410核心板 410a開孔 420外層線路板 430外層線路板 432 SMT銅墊 440錫膏 • 460導通孔 500内埋式元件 14Thereafter, the subsequent step of solder ball processing and surface treatment is performed to form a solder ball 72 on the copper crucible 322 exposed by the solder resist opening I, and a protective layer 82 is formed on the exposed copper mat, for example, , nickel-gold, organic soldering agent (dedication, OSP). The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention are within the scope of the present invention. [Simple description of the diagram] 12 201110836 The first figure shows the schematic diagram of the conventional embedded tree silk surface. FIG. 9 is a schematic view showing a method of fabricating a buried component substrate according to a preferred embodiment of the present invention. [Main component symbol description] 1 core circuit board lb lower surface l〇a conductor pattern 12a connection copper crucible 14a fine line 16 conductive via structure 112 conductive bump 2 carrier 20 substrate 212 conductive bump 220 circuit pattern 224 fine line 3 carrier 30 substrate 300 buried component 312a alloy bump 322 copper 塾 la upper surface 10 core substrate l 〇 b wire pattern 12b connection copper pad 14b fine line 18 opening 112a alloy plug 22 surface steel layer 212a alloy plug Plug 222 copper 塾 32 surface steel layer 312 conductive bump 320 circuit pattern 324 fine line 13 201110836 332 copper pad 4 intermediate joint material 48 through hole 5 intermediate joint material 60 alloy interface 70 solder resist layer 70a solder joint opening 72 tin Ball 80 solder resist layer 80a solder mask opening 82 protective layer • 400 buried component substrate C 410 core board 410a opening 420 outer circuit board 430 outer circuit board 432 SMT copper pad 440 solder paste • 460 via hole 500 Buried element 14