05 9 8TWF.DOC/Frank/002 A7 B7 五、發明説明（I ) 本發明是有關於一種應用於靜態隨機存取記憶體 (SRAM)單元中薄膜電晶體的構造及其製造方法，且特別是 有關於一種具有低電流及低內連線電阻之薄膜電晶體的構 造及其製造方法。 第1圖表示一種靜態隨機存取記憶體單元10。靜態隨 機存取記憶體單元10包括一第一驅動器（driver)Νι及第二 驅動器N2，且驅動器仏及1是屬下拉N型金氧半電晶體 (NMOS)元件。K的源極12和N2的源極14均連接一個接地 的參考電壓Vss。N2的汲極16和^的閘極18相連接。仏的 汲極20和N2的閘極22相連接。第1圖中的靜態隨機存取記 憶體單元10也包括兩個負載元件1^和L2。負載元件匕和L2 的一端24和26同時連接至一參考電壓Vee，且另一端28及 30分別和N!的汲極20及N2的汲極16連接。相對於參考電 壓Vss而言，參考電壓爲陽極。 靜態隨機存取記憶體單元10也包括兩個額外的N型金 氧半電晶體元件仏和N4，是爲轉移電晶體。仏和N4的閘極 32及34分別連接至一字元線，此字元線命名爲WORD，源 極36及38分別連接至命名爲BIT及ΪΪΥ的位元線，而汲極 經濟部中央標準局員工消費合作社印製 〈請先閲讀背面之注意事項再填寫本頁) 40和42則分別和1及N2的汲極20、16相連接。 對該單元寫入時，資料DATA(邏輯“1”或“G”）安置在線 BIT，資料DATA安置在線ΪΪΥ。之後即由線WORD主導。讀05 9 8TWF.DOC / Frank / 002 A7 B7 V. Description of the invention (I) The present invention relates to a structure and manufacturing method of a thin film transistor applied in a static random access memory (SRAM) cell, and in particular It relates to a structure and manufacturing method of a thin film transistor with low current and low interconnection resistance. FIG. 1 shows a static random access memory unit 10. The static random access memory unit 10 includes a first driver N1 and a second driver N2, and drivers Q1 and N1 are pull-down N-type metal oxide semiconductor (NMOS) devices. The source electrode 12 of K and the source electrode 14 of N2 are both connected to a grounded reference voltage Vss. The drain 16 of N2 is connected to the gate 18 of ^. The drain 20 is connected to the gate 22 of N2. The static random access memory unit 10 in FIG. 1 also includes two load elements 1 ^ and L2. One end 24 and 26 of the load element D2 and L2 are simultaneously connected to a reference voltage Vee, and the other ends 28 and 30 are connected to the drain 20 of N! And the drain 16 of N2, respectively. Relative to the reference voltage Vss, the reference voltage is the anode. The static random access memory cell 10 also includes two additional N-type metal oxide semi-transistor elements Q4 and N4, which are transfer transistors. Gates 32 and 34 of Qian and N4 are connected to a word line, respectively, this word line is named WORD, sources 36 and 38 are connected to bit lines named BIT and ΪΪΥ, respectively, and the central standard of the Ministry of Economic Affairs Printed by the Bureau Staff Consumer Cooperative (please read the precautions on the back before filling out this page) 40 and 42 are connected to the 1 and N2 drains 20 and 16, respectively. When writing to this unit, the data DATA (logic "1" or "G") is placed on line BIT, and the data DATA is placed on line ΪΪΥ. After that, it is dominated by line WORD. read
取的動作是藉由線BIT和ΪΙΪ的預充電開始，然後由線WORD 主導，且線BIT或ΪΪΓ將藉由下拉電晶體仏或N2之一來放 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） F.DOC/Frank/002 A7 B7 五、發明説明（义） όI — {請先閲讀背面之注意事項再填寫本頁) 負載兀件Li和L2的目的是防止在Νι和N2的汲極16、 20產生電荷遺漏，負載元件1^和L2可爲多晶系矽電阻或P 型金氧半電晶體（PMOS)元件。在本例中負載元件1^和1^爲P 型金氧半電晶體元件，該元件的源極連接至參考電壓Vcc， 而汲極則連接至1和1的汲極20和16。匕和^中P型金 氧半電晶體的閘極分別和下拉驅動器1和N2的閘極相連 接。 爲減低靜態隨機存取記憶體單元10的尺寸以及具有更 進一步的應用，必須要有更高的密度及更低的等待 (standby)電流，所以負載元件1^和L2可能是P型薄膜電晶 體。本例中，靜態隨機存取記憶體單元是眾所周知的一種 薄膜電晶體靜態隨機存取記憶體單元。 經濟部中央標準局員工消費合作社印製 第2a圖是一種排成列45之薄膜電晶體靜態隨機存取 記憶體單元，其中的一個薄膜電晶體靜態隨機存取記憶體 單元50係以較詳細之圖例表示。第2b圖是以更詳細的圖例 來顯示該單元。單元50的負載元件命名爲P4D P2，且是薄 膜電晶體P型金氧半電晶體。卩!及？2元件的源極52、54 和Vec相連接，汲極56、58分別和仏及N2的汲極20、16 相連接（也分別和心及N4的汲極40、42相連接），而閘極 60、62則分別和1及仏的閘極18、22相連接。寄生電阻 Rm在薄膜電晶體源極52、54及V。。之間形成一薄膜電晶體 內連接阻抗。如第2a圖所示，在列45中的每一記憶單元均 藕接有額外的寄生電阻。每一記憶單元50的源極寄生 電阻稱爲，其中RVc如圖所示，是由一個或數個Rvcc 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 經濟部中央標準局員工消費合作社印製 05 98TWF.DOC/Frank/002 A7 ____B7 五、發明説明（彡） 組成。 接腳70包括卩1和1，當Ρ，導通時，接腳70的電流以 Ion表示，當P!關閉時，接腳70的電流以1。〃表示。（同樣 的定義也可應用在由P2和N2組成之接腳80中）。需要的 話，必須使1。：>値較大而1。〃的値較小，以使Ιπ/Ι。”的比値 變大。同樣地，最好能使連接在V。。的寄生電阻値越小 越好。減少寄生電阻Rm：的値，可以降低Vex和薄膜電晶體 的源極52、54間的壓降。寄生電阻Rm：的値愈小，則通過 寄生電阻Rw所造成的壓降也愈小。如此可增強電路的運作 及減少電源的浪費。 經過寄生電阻Rm：造成的壓降會降低對薄膜電晶體Ρ! 及？2的源極52、54的電壓供應。在源極52和54的電壓可 表示爲V^-iR%。。，其中i爲通過寄生電阻的有效電流。 由於寄生電阻RV。所造成的壓降iRVe，會導致薄膜電晶體 卩!及P2的閘極到源極電壓Vgs以及汲極到源極電壓Vds的減 少，故當薄膜電晶體的源極和汲極的內連線愈長，例如高 容量的靜態存機存取記憶體晶片，其所造成的寄生內連線 電阻値也愈大，如此會大幅降低電路的運作效率。 在需要大量省電的應用上，例如極低的等待電流，必 須使薄膜電晶體有極低的關閉電流（1。〃），例如1。〃小於 IpA。要製造一個有低關閉電流的薄膜電晶體，必須使薄膜 電晶體的源極和汲極之間的通道夠薄，例如通道的厚度爲 200A。 從第3a-3d圖的描述將可明顯地瞭解，薄膜電晶體的 5 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公" ----------〇------IT------ο (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印褽 0598TWF.DOC/Frank/002 A7 —___B7 五、發明説明（ψ ) 通道、源極和汲極係形成在同一層。薄膜電晶體的源極和 汲極分別連接至其它的元件，例如在接腳70處薄膜電晶體 P!的汲極56和N型金氧半電晶體元件N!的汲極20相連接， 而薄膜電晶體P!的源極52和Vex相連接。 要使薄膜電晶體內連線電阻値降低，薄膜電晶體？1的 源極52和汲極56的厚度必須增加。因爲薄膜電晶體？!的 源極52、汲極56和通道均在相同的主體層（body layer) 中，如此一來，薄膜電晶體P!的源極52、汲極56和通道 均爲相同的厚度。一般而言，有著極低關閉電流的薄膜電 晶體，必須使用極薄的膜層（例如通道的厚度是200A)，且 源極和汲極也必須有極薄的膜層。但是源極和汲極區太薄 會造成薄膜電晶體內連線電阻値變大，使電路的運作效率 降低。 第3a-3d圖表示傳統薄膜電晶體靜態隨機存取記憶體 結構100的形成方式，該結構爲第2b圖中薄膜電晶體靜態 隨機存取記憶體單元50的其中一處接腳，例如接腳70。如 圖3a所示，薄膜電晶體靜態隨機存取記憶體100有一 N型 矽基底112，且在該基底112上形成一 P井（P-wel 1)114。 N+汲極116和N+源極118在P井114中形成，並被通道120 分開。在薄膜電晶體靜態隨機存取記憶體100結構上形成 一氧化層122。在汲極116之上，部分氧化層112被蝕刻 (etch)而形成一缺口 124。第一多晶矽層126沈積在氧化層 122和缺口 124之上。 如第3b圖所示，定義（pattern)第一多晶矽層126，並 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 〇 ^ 0 (請先閲讀背面之注意事項再填寫本頁) DOC/Frank/002 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（艾） 摻入N型離子128，使在通道120上方形成N+閘極130以及 在汲極116露出的部份（例如在缺口 124上）形成N+汲極接點 140。汲極116、源極118及閘極130相當於第1圖及第2 圖中之t下拉電晶體的汲極20、源極12及閘極18。接著， 將厚的內聚合介電層（inter-poly-dielectric layer)145 形成在閘極130、氧化層122及汲極接點14G之上，再進行 微影而露出N+汲極接點140。利用內聚合介電層145使得第 2b圖中的薄膜電晶體P!和第2b圖中位於薄膜電晶體P:之下 的驅動器K絕緣。定義內聚合介電層145，形成一個露出 部分N+汲極接點140的缺口 146。 第2b圖中的薄膜電晶體Pt將形成在內聚合介電層145 之上，其方法如下。如第3C圖所示，在內聚合介電層145 及N+汲極接點140曝露的部份之上，形成一第二多晶矽層 147，且第二多晶矽層147重度摻雜N型離子149。請參照 第3d圖，定義N型第二多晶矽層147，形成N+第二多晶矽 接點155及N+薄膜電晶體閘極160。N+第二多晶矽接點155 和N+汲極接點140電性藕接。 在N+第二多晶矽接點155、薄膜電晶體閘極160及保留 的內聚合介電層145上，形成一薄膜電晶體氧化層165。對 薄膜電晶體氧化層165進行圖案定義和蝕刻，使部分N+第 二多晶矽接點155能露出來。將第三多晶矽層170沈積在多 晶矽層147之上，利用N+第二多晶矽接點155使第三多晶矽 層170和第二多晶矽層147導接。 在經過微影的薄膜電晶體氧化層165上形成之第三多 7 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐〉 ό—— (請先聞讀背面之注$項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 05 9 8TWF.DOC/Frank/002 A7 B7 五、發明説明（A ) 晶矽層170，係作爲一薄膜電晶體的主體層，並摻雜有N 型離子。 在N型薄膜電晶體主體層170沈積之後，將額外的P 型離子175選擇性的植入主體層170，形成薄膜電晶體的P+ 汲極180和源極185。藉由一薄膜電晶體通道190將薄膜電 晶體的P+汲極180和源極185分開，其中，P+汲極180—部 份位於N+接點155之上，且P+源極185—部份位於N+薄膜電 晶體閘極160之上。請參照第2b圖，N+第二多晶矽接點155 是用來連接下拉N型金氧半電晶體N,的汲極20和薄膜電晶 體Pi的汲極56。 如第3d圖所示，在薄膜電晶體主體層170中，汲極 180、源極185和通道190的厚度均相同。因此無法利用減 少寄生內連線電阻値來達到一低關閉電流的薄膜電晶體， 因爲低關閉電流的薄膜電晶體需要薄的通道，而低的寄生 內連線電阻値則須要厚的源極和汲極。 於是，如何發展一種方法能製造同時具有低關閉電流 及低寄生內連線電阻的薄膜電晶體，例如一薄膜電晶體靜 態隨機存取記憶體，已成爲一重要的課題。 因此，本發明的主要目的就是在提供一種有著低關閉 電流以及低內連線電阻的薄膜電晶體之結構與製造方法。 依照本發明的薄膜電晶體有薄的通道區以得到低的關閉_ 流，以及厚的汲極和源極區以得到低的內連線電阻。本發 明的製程使用一局部氧化技術，且不需要額外的光章層， 所以本發明的薄膜電晶體在製造上不會增加額外的費用。 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ο II (請先閲讀背面之注意事項再填寫本筲) 訂 0598TWF.DOC/Frank/002 A7 0598TWF.DOC/Frank/002 A7 經濟部中央標準局員工消費合作社印裝 ------B7_ 五、發明説明^Γ5 '~ - 爲達成本發明之上述和其他目的，提出一種薄膜電晶 體的製造方法，包括下列步驟：薄膜電晶體閘極多晶矽層 (桌一多晶砂層）包括一閘極和一連接至一驅動器汲極之汲 極。一薄膜電晶體閘極氧化層形成在第二多晶矽薄膜電晶 體閘極層之上；在薄膜電晶體閘極氧化層中形成一缺口。 使薄膜電晶體主體層能和汲極接點接觸並導電；並在 閘極氧化層和部份汲極接點缺口上沈積一厚的非晶系砂薄 膜電晶體主體層；利用熱處理將薄膜電晶體主體層轉變爲 高品質的多晶矽結構。 經過微影步驟中簡單的氧化反應和氮化矽的化學氣相 沈積（chemical vapor deposition)後，形成一氮化物窗 (nitride window)，氮化物窗曝露了部份當作薄膜電晶體 通道的主體層《薄膜電晶體主體層露出的部份，如薄膜電 晶體的通道，經由氧化反應可減少通道的厚度，並被形成 的通道氧化物所覆蓋。將薄膜電晶體主體層殘留的氮化物 層除去後，利用離子植入法可形成源極和汲極。源極形成 在通道的一邊，汲極形成在通道的另一邊。當P+離子摻入 薄膜電晶體的源極和汲極時，厚的薄膜電晶體通道氧化物 層可當作一個遮蔽物。之後，再將薄膜電晶體通道氧化物 層除去。在通道摻入雜質，可達到調整薄膜電晶體臨限電 壓（threshold voltage)的目的。如此一來，可使薄膜電晶 體有著薄的通道區且有厚的源極、汲極和內連線區。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 9 本紙張尺度適用中國國家標準（CNS〉A4規格（21〇><297公釐） (請先閲讀背面之注意事項再填寫本頁)The action is taken by the pre-charging of the line BIT and ΪΙΪ, and then dominated by the line WORD, and the line BIT or ΪΪΓ will be placed by pulling down one of the transistors or N2. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) F.DOC / Frank / 002 A7 B7 V. Invention description (meaning) όI — {Please read the precautions on the back before filling this page) The purpose of the load elements Li and L2 is to prevent The drains of N2 and Drains 16 and 20 produce charge leakage, and the load elements 1 ^ and L2 may be polycrystalline silicon resistors or P-type metal oxide semiconductor (PMOS) elements. In this example, the load elements 1 ^ and 1 ^ are P-type metal oxide semi-transistor elements whose source is connected to the reference voltage Vcc and the drain is connected to the drains 20 and 16 of 1 and 1. The gates of the P-type metal oxide semi-transistors in Dagger and ^ are connected to the gates of the pull-down drivers 1 and N2, respectively. In order to reduce the size of the static random access memory cell 10 and have further applications, it is necessary to have higher density and lower standby current, so the load elements 1 ^ and L2 may be P-type thin film transistors . In this example, the static random access memory cell is a well-known thin film transistor static random access memory cell. Figure 2a printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is a line of 45 thin film transistor static random access memory units. One of the thin film transistor static random access memory units 50 is described in more detail. Legend representation. Figure 2b shows the unit with a more detailed illustration. The load element of unit 50 is named P4D P2, and is a thin film transistor P-type metal oxide semitransistor. That is! And? 2 The source 52, 54 and Vec are connected, the drains 56, 58 are connected to the drains 20 and 16 of N2 and N2 (also connected to the drains 40 and 42 of N4 and N4, respectively), and the gate The poles 60 and 62 are connected to the gates 18 and 22 of 1 and 250, respectively. The parasitic resistance Rm is at the source 52, 54 and V of the thin film transistor. . A thin film transistor is formed between the connection impedances. As shown in Figure 2a, each memory cell in column 45 is coupled with an additional parasitic resistance. The source parasitic resistance of each memory cell 50 is called, where RVc is shown in the figure, which is composed of one or several Rvcc. 4 This paper scale is applicable to China National Standard (CNS) A4 specification (210X 297 mm) Central Standard of the Ministry of Economy Printed by Bureau Staff Consumer Cooperatives 05 98TWF.DOC / Frank / 002 A7 ____B7 V. Description of invention (彡) Composition. Pin 70 includes 卩 1 and 1, when P, is on, the current of pin 70 is represented by Ion, when P! Is off, the current of pin 70 is 1. 〃 Show. (The same definition can also be applied to pin 80 consisting of P2 and N2). If necessary, it must be 1. : ≫ Value is larger and 1. The value of 〃 is small to make Ιπ / Ι. "The ratio value becomes larger. Similarly, it is better to make the parasitic resistance value connected to V .. The smaller the value, the better. Reducing the parasitic resistance value Rm: can reduce the value between Vex and the source 52, 54 of the thin film transistor Voltage drop. Parasitic resistance Rm: The smaller the value, the smaller the voltage drop caused by the parasitic resistance Rw. This can enhance the operation of the circuit and reduce the waste of power. After the parasitic resistance Rm: the voltage drop will decrease The voltage supply to the source 52, 54 of the thin film transistor P! And? 2. The voltage at the source 52 and 54 can be expressed as V ^ -iR% ..., where i is the effective current through the parasitic resistance. Due to the parasitic Resistance RV. The resulting voltage drop iRVe will cause the thin-film transistors! And the gate-to-source voltage Vgs and the drain-to-source voltage Vds of P2 to decrease, so when the source and drain of the thin film transistor The longer the interconnection, such as the high-capacity static memory access memory chip, the larger the parasitic interconnection resistance value, which will greatly reduce the operating efficiency of the circuit. In applications that require a large amount of power saving , Such as extremely low waiting current, the thin film The body has a very low off current (1.〃), for example 1.〃 is less than IpA. To manufacture a thin film transistor with a low off current, the channel between the source and the drain of the thin film transistor must be thin enough, For example, the thickness of the channel is 200A. From the description in Figures 3a-3d, it will be apparent that the 5 paper scales of the thin-film transistors are applicable to the Chinese National Standard (CNS) A4 specification (210X297 public " ------ ---- 〇 ------ IT ------ ο (Please read the precautions on the back before filling this page) Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Printed 0598TWF.DOC / Frank / 002 A7 —___ B7 V. Description of Invention (ψ) The channel, source and drain are formed on the same layer. The source and drain of the thin film transistor are connected to other components, such as the thin film transistor P at pin 70! The drain electrode 56 is connected to the drain electrode 20 of the N-type metal oxide semi-transistor element N !, and the source electrode 52 of the thin film transistor P! Is connected to Vex. To reduce the wiring resistance value of the thin film transistor Transistors? The thickness of the source 52 and the drain 56 must be increased. Because of the thin film transistor ?! The source 52, the drain 56 and the pass The channels are all in the same body layer, so that the source 52, the drain 56 and the channel of the thin-film transistor P! Have the same thickness. Generally speaking, thin-film transistors with very low off current For crystals, a very thin film layer (for example, the thickness of the channel is 200A) must be used, and the source and drain electrodes must also have very thin film layers. However, if the source and drain regions are too thin, it will cause the interconnection of the thin film transistor The resistance value becomes larger, which reduces the operating efficiency of the circuit. Figures 3a-3d show the formation of a conventional thin film transistor static random access memory structure 100, which is the thin film transistor static random access memory in figure 2b. One of the pins of unit 50, such as pin 70. As shown in FIG. 3a, the thin film transistor static random access memory 100 has an N-type silicon substrate 112, and a P-well (P-wel 1) 114 is formed on the substrate 112. The N + drain 116 and N + source 118 are formed in the P-well 114 and separated by the channel 120. An oxide layer 122 is formed on the structure of the thin film transistor static random access memory 100. Above the drain 116, a portion of the oxide layer 112 is etched to form a notch 124. The first polysilicon layer 126 is deposited over the oxide layer 122 and the gap 124. As shown in Figure 3b, the pattern of the first polysilicon layer 126 is defined, and 6 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). 0 ^ 0 (Please read the precautions on the back first (Fill in this page) DOC / Frank / 002 A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of Invention (Ai) N-type ion 128 is incorporated to form an N + gate 130 above the channel 120 and a drain The exposed portion of 116 (for example, on the notch 124) forms the N + drain contact 140. The drain 116, the source 118, and the gate 130 correspond to the drain 20, the source 12, and the gate 18 of the t pull-down transistor in FIGS. 1 and 2. Next, a thick inter-poly-dielectric layer 145 is formed on the gate 130, the oxide layer 122, and the drain contact 14G, and then lithography is performed to expose the N + drain contact 140. The interpolymerized dielectric layer 145 is used to insulate the thin film transistor P! In Fig. 2b and the driver K located under the thin film transistor P: in Fig. 2b. The inner polymeric dielectric layer 145 is defined to form a gap 146 exposing a portion of the N + drain contact 140. The thin film transistor Pt in FIG. 2b will be formed on the inner polymeric dielectric layer 145 by the following method. As shown in FIG. 3C, a second polysilicon layer 147 is formed on the exposed portion of the inner polymeric dielectric layer 145 and the N + drain contact 140, and the second polysilicon layer 147 is heavily doped with N Type ion 149. Referring to FIG. 3d, an N-type second polysilicon layer 147 is defined to form an N + second polysilicon contact 155 and an N + thin film transistor gate 160. The N + second polysilicon contact 155 and the N + drain contact 140 are electrically coupled. A thin film transistor oxide layer 165 is formed on the N + second polysilicon contact 155, the thin film transistor gate 160, and the remaining inner polymeric dielectric layer 145. The thin film transistor oxide layer 165 is patterned and etched so that part of the N + second polysilicon contact 155 can be exposed. A third polysilicon layer 170 is deposited on the polysilicon layer 147, and the third polysilicon layer 170 and the second polysilicon layer 147 are connected by using N + second polysilicon contacts 155. The third-largest 7-sheet paper formed on the lithographic thin film transistor oxide layer 165 conforms to the Chinese National Standard (CNS> A4 specification (210X297mm) ό—— (please read the $ item on the back first (Fill in this page) Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Printed 05 9 8TWF.DOC / Frank / 002 A7 B7 V. Description of Invention (A) The crystalline silicon layer 170 is used as the main layer of a thin-film transistor and is doped Mixed with N-type ions. After the N-type thin-film transistor body layer 170 is deposited, additional P-type ions 175 are selectively implanted into the body layer 170 to form the P + drain 180 and source 185 of the thin-film transistor. A thin film transistor channel 190 separates the P + drain 180 and the source 185 of the thin film transistor, where P + drain 180—part is located above the N + contact 155, and P + source 185—part is located at the N + thin film transistor Above the crystal gate 160. Please refer to FIG. 2b, the N + second polysilicon contact 155 is used to connect the drain 20 of the pull-down N-type metal oxide semi-transistor N, and the drain 56 of the thin film transistor Pi. As shown in FIG. 3d, in the thin film transistor body layer 170, the thickness of the drain electrode 180, the source electrode 185, and the channel 190 They are all the same. Therefore, it is impossible to reduce the parasitic interconnect resistance to achieve a low-off-current thin film transistor, because the low-off current thin-film transistor requires a thin channel, and the low parasitic interconnect resistance value needs to be thick Source and drain. Therefore, how to develop a method to manufacture thin film transistors with low off current and low parasitic interconnect resistance, such as a thin film transistor static random access memory, has become an important issue Therefore, the main purpose of the present invention is to provide a structure and manufacturing method of a thin film transistor with low turn-off current and low interconnect resistance. The thin film transistor according to the present invention has a thin channel region to obtain low turn-off_ Current, and thick drain and source regions to obtain low interconnect resistance. The process of the present invention uses a local oxidation technique and does not require an additional optical layer, so the thin film transistor of the present invention is not Additional costs will be added. 8 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ο II (Please read the back page first (Please fill in this note if necessary) Order 0598TWF.DOC / Frank / 002 A7 0598TWF.DOC / Frank / 002 A7 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ------ B7_ V. Description of Invention ^ Γ5 '~- In order to achieve the above and other objects of the invention, a method for manufacturing a thin film transistor is proposed, which includes the following steps: a thin film transistor gate polysilicon layer (a polysilicon layer) includes a gate and a driver connected to a driver drain Drain. A thin-film transistor gate oxide layer is formed on the second polysilicon thin-film transistor gate layer; a gap is formed in the thin-film transistor gate oxide layer. The thin film transistor body layer can be in contact with the drain contact and conduct electricity; and a thick amorphous sand thin film transistor body layer is deposited on the gate oxide layer and part of the drain contact gap; The crystal body layer is transformed into a high-quality polysilicon structure. After a simple oxidation reaction in the lithography step and chemical vapor deposition of silicon nitride (nitride window), a nitride window is formed. The nitride window exposes a portion that serves as the main body of the thin film transistor channel The exposed part of the main layer of the thin film transistor, such as the channel of the thin film transistor, can reduce the thickness of the channel through the oxidation reaction and be covered by the formed channel oxide. After removing the remaining nitride layer of the thin film transistor body layer, the source and drain can be formed by ion implantation. The source is formed on one side of the channel, and the drain is formed on the other side of the channel. When P + ions are incorporated into the source and drain of the thin film transistor, the thick thin film transistor channel oxide layer can be used as a shield. After that, the thin film transistor channel oxide layer is removed. Doping impurities in the channel can achieve the purpose of adjusting the threshold voltage of the thin film transistor. In this way, the thin film transistor can have a thin channel region and thick source, drain and interconnect regions. In order to make the above-mentioned and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment will be given below, in conjunction with the attached drawings. Specifications (21〇 < 297mm) (Please read the notes on the back before filling this page)
05 98TWF.DOC/Frank/002 A7 05 98TWF.DOC/Frank/002 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（？） 細說明如下： 圖式之簡單說明： 第1圖是一種習知的靜態隨機存取記憶體單元之電路 圖； 第2a圖是一種習知的薄膜電晶體靜態隨機存取記憶體 單元之電路圖； 第2b圖是一出現在第2a圖中之傳統的薄膜電晶體靜 態隨機存取記憶體單元更詳細的電路圖； 第3a-3d圖是製造一種傳統薄膜電晶體的製造流程剖 面圖；以及 第4-10圖是依照本發明實施例製造之一種薄膜電晶體 的製造流程剖面圖。 實施例 本發明的重點在於薄膜電晶體的結構和製造方法，並 且以應用在靜態隨機存取記憶體單元上爲例。依照本發明 所製造的薄膜電晶體，有著可減少關閉電流的薄通道，同 時也有可減少寄生內連線電阻的汲極區和源極區。並且， 薄膜電晶體中內連線電阻値的減少並不會降低薄膜電晶體 的效率。 依照本發明之較佳實施例之描述自第4圖開始，請參 照第4圖，一矽晶圓（wafer)200包含有被一厚的內聚合介 電層145覆蓋的一驅動元件架構210。內聚合介電層145 及驅動元件架構210類似於第3a-3d圖中顯示之習知薄膜 電晶體靜態隨機存取記憶體架構100的內聚合介電層145 ό-I (請先閲讀背面之注意事項再填寫本頁) ，1Τ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 05 9 8TWF.DOC/Frank/002 05 9 8TWF.DOC/Frank/002 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3 ) 及N型金氧半電晶體驅動器，也就是說，該驅動元件架構 210的製程和前述第3a和3b圖所描述的製程有關。驅動元 件架構210包含有〜矽基底112，而該矽基底中形成有一 p 井114。利用離子植入法，將例如n型離子植入1>井u4中， 形成N+汲極116與源極118，且汲極116和源極118被通道 120分開。氧化層122覆蓋在矽晶圓200之上，部分的氧化 層122被除去，而曝露出部份的汲極116。第一多晶矽層（圖 3a中之第一多晶矽層126)沈積在氧化層122和汲極116露 出的部分之上。 對第一多晶矽層進行微影，並摻入N型離子，使得在 通道120上方形成N+閘極130，且在汲極116露出的部份形 成N+汲極接點140。接著在閘極130和氧化層122上形成內 聚合介電層145，並對內聚合介電層145進行微影，使N+ 汲極接點140曝露出來。以圖4所示爲例，內聚合介電層 145的厚度約爲2000A。 一厚的第二多晶矽層147沈積在內聚合介電層145 上，作爲薄膜電晶體之閘極層，其厚度例如約爲1000A。 接著利用離子植入法，把N型離子149植入第二多晶矽薄膜 電晶體閘極層147中，形成雜質濃度約爲l〇2eciif3的重度摻 雜之N+第二多晶矽薄膜電晶體閘極層147。離子149例如爲 砷離子，且離子植入時之流量密度約爲l〇15cnf2，能量約爲 80KeV 。 請參照第5圖，定義重度摻雜之N離子的第二多晶矽薄 膜電晶體閘極層147，形成一 N+第二多晶砂薄膜電晶體汲 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ΟII (請先閲讀背面之注意事項再填寫本頁) 訂 05 9 8TWF.DOC/Frank/002 A7 B7 五、發明説明（/P ) 極接點155及一 N+薄膜電晶體閘極160。定義N+第二多晶矽 層147的步驟是先在N+第二多晶矽薄膜電晶體閘極層147 上形成一罩幕（mask)，然後進行蝕刻，例如可以使用六氟 乙院（C2F6)進行乾蝕刻或溼触刻。 接著，例如利用化學氣相沈積法，將薄的薄膜電晶體 閘極氧化層165沈積在晶圓200上。如圖所示，藉由化學氣 相沈積法形成在晶圓200表面的薄膜電晶體閘極氧化層 165，其輪廓與晶圓200表面的輪廓一致。其表面較佳是爲 光滑的，且厚度約爲300A。對薄膜電晶體氧化層165進行 圖案轉移和蝕刻，形成一缺口 167，該缺口 167曝露出部份 的N+第二多晶矽接點155。露出的N+第二多晶矽接點155 用以連接其後形成之驅動器的汲極和薄膜電晶體之汲極。 請參照第6圖，一非晶系矽薄膜，如第三多晶矽薄膜 電晶體主體層170 ’沈積在薄膜電晶體閘極氧化層i65的光 滑表面上。多晶矽主體層17G的厚度係設計爲可使源極和 卞及極接點具有低的片電阻（sheet resistance)，當第三多 晶砂薄膜電晶體主體層170的厚度增加，接點的片電阻値 就會降低（如第2a、2b圖中的Rvee)。第三多晶砂薄膜電晶 體主體層170的厚度例如約爲1GG0A。 將第二多晶砂薄膜電晶體主體層置於低溫下，以 一段長時間進行回火（anneal)。回火的時間例如約爲12小 時，溫度例如約爲600 °C。回火後使第三多晶砂薄膜電晶 體主體層170轉變爲表面平滑的高品質多晶系矽薄膜。 接著經由簡單的氧化反應，在N型第三多晶砂層170 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） ο II (請先閲讀背面之注意事項再填寫本頁)05 98TWF.DOC / Frank / 002 A7 05 98TWF.DOC / Frank / 002 A7 Printed B7 by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (?) The detailed description is as follows: Brief description of the diagram: The first picture is A circuit diagram of a conventional static random access memory cell; Figure 2a is a circuit diagram of a conventional thin film transistor static random access memory cell; Figure 2b is a conventional thin film that appears in Figure 2a A more detailed circuit diagram of a transistor static random access memory cell; Figures 3a-3d are cross-sectional views of a manufacturing process for manufacturing a traditional thin film transistor; and Figures 4-10 are a thin film transistor manufactured according to an embodiment of the present invention Cross-sectional view of the manufacturing process. Embodiments The focus of the present invention is on the structure and manufacturing method of thin film transistors, and it is applied to a static random access memory cell as an example. The thin film transistor manufactured according to the present invention has a thin channel that can reduce the off current, and also has a drain region and a source region that can reduce parasitic interconnect resistance. Moreover, the reduction in the resistance value of the interconnection in the thin film transistor does not reduce the efficiency of the thin film transistor. The description of the preferred embodiment according to the present invention starts from FIG. 4, please refer to FIG. 4, a silicon wafer (wafer) 200 includes a driving element structure 210 covered by a thick inner polymer dielectric layer 145. The interpolymerized dielectric layer 145 and the driving element architecture 210 are similar to the internally polymerized dielectric layer 145 of the conventional thin film transistor static random access memory architecture 100 shown in FIGS. 3a-3d (please read the back (Notes and then fill out this page), 1T paper size is applicable to China National Standard (CNS) Α4 specifications (210X 297 mm) 05 9 8TWF.DOC / Frank / 002 05 9 8TWF.DOC / Frank / 002 Central Bureau of Standards A7 B7 printed by the Employee Consumer Cooperative. V. Description of invention (3) and N-type metal oxide semi-transistor driver, that is to say, the manufacturing process of the driving element architecture 210 is related to the manufacturing process described in FIGS. 3a and 3b. The driving element architecture 210 includes a silicon substrate 112, and a p-well 114 is formed in the silicon substrate. Using the ion implantation method, for example, n-type ions are implanted into the well u4 to form the N + drain 116 and the source 118, and the drain 116 and the source 118 are separated by the channel 120. The oxide layer 122 covers the silicon wafer 200, part of the oxide layer 122 is removed, and part of the drain 116 is exposed. A first polysilicon layer (first polysilicon layer 126 in FIG. 3a) is deposited on the exposed portions of the oxide layer 122 and the drain 116. The first polysilicon layer is photolithographically doped with N-type ions, so that an N + gate 130 is formed above the channel 120, and an N + drain contact 140 is formed at the exposed portion of the drain 116. Next, an inner polymerized dielectric layer 145 is formed on the gate electrode 130 and the oxide layer 122, and the inner polymerized dielectric layer 145 is lithographically exposed to expose the N + drain contact 140. Taking the example shown in FIG. 4, the thickness of the inner polymeric dielectric layer 145 is about 2000A. A thick second polysilicon layer 147 is deposited on the inner polymeric dielectric layer 145 as a gate layer of the thin film transistor, and its thickness is, for example, about 1000A. Next, by ion implantation, N-type ions 149 are implanted into the second polysilicon thin film transistor gate layer 147 to form a heavily doped N + second polysilicon thin film transistor with an impurity concentration of about lO2eciif3 Gate layer 147. The ion 149 is, for example, arsenic ion, and the flow density at the time of ion implantation is about 1015cnf2, and the energy is about 80KeV. Please refer to FIG. 5 to define the second polysilicon thin film transistor gate layer 147 of heavily doped N ions to form an N + second polycrystalline sand thin film transistor. The paper size is applicable to China National Standard (CNS) A4 Specifications (210X297mm) ΟII (Please read the precautions on the back before filling this page) Order 05 9 8TWF.DOC / Frank / 002 A7 B7 Fifth, the invention description (/ P) pole contact 155 and a N + thin film transistor Gate 160. The step of defining the N + second polysilicon layer 147 is to first form a mask on the N + second polysilicon thin film transistor gate layer 147, and then perform etching, for example, hexafluoroethylene (C2F6) can be used Perform dry etching or wet etching. Next, for example, a thin film transistor gate oxide layer 165 is deposited on the wafer 200 using chemical vapor deposition. As shown in the figure, the thin film transistor gate oxide layer 165 formed on the surface of the wafer 200 by the chemical vapor deposition method has the same contour as the contour of the surface of the wafer 200. The surface is preferably smooth and has a thickness of about 300A. The thin film transistor oxide layer 165 is pattern-transferred and etched to form a notch 167 that exposes part of the N + second polysilicon contact 155. The exposed N + second polysilicon contact 155 is used to connect the drain of the driver and the drain of the thin film transistor formed later. Referring to FIG. 6, an amorphous silicon thin film, such as a third polysilicon thin film transistor body layer 170 'is deposited on the smooth surface of the thin film transistor gate oxide layer i65. The thickness of the polysilicon body layer 17G is designed to provide a low sheet resistance at the source and junctions. When the thickness of the third polysilicon thin film transistor body layer 170 increases, the sheet resistance of the contact The value will decrease (as in Rvee in Figures 2a and 2b). The thickness of the third polycrystalline sand thin film electric crystal body layer 170 is, for example, about 1GG0A. The second polycrystalline sand thin film transistor main body layer is placed at a low temperature and annealed for a long period of time. The tempering time is, for example, about 12 hours, and the temperature is, for example, about 600 ° C. After tempering, the third polycrystalline sand thin film electric crystal body layer 170 is transformed into a high-quality polycrystalline silicon thin film with a smooth surface. Then, after a simple oxidation reaction, the paper standard of the N-type third polycrystalline sand layer 170 applies to the Chinese National Standard (CNS) Α4 specification (210X297mm) ο II (please read the precautions on the back before filling this page)
、1T 經濟部中央標準局貝工消費合作社印製 05 98TWF.DOC/Frank/002 A7 B7 五、發明説明（I丨） 上形成一薄的薄膜電晶體遮蔽氧化層220，其厚度例如約 爲100人。 請參照第7圖，例如利用化學氣相沈積法，將氮化矽 層230覆蓋在晶圓200上，厚度例如約爲1000A。然後進行 微影步驟，使光阻層235覆蓋住將做爲薄膜電晶體通道190 之外的區域。對未被光阻層235覆蓋的區域進行蝕刻，將 氮化矽層230以及遮蔽氧化層220蝕刻後，在N型第三多晶 矽薄膜電晶體主體層170上形成一空窗（window)240。 請參照第8圖，去除光阻層235，接著進行熱氧化法 (thermal oxidation)。對在空窗240中之薄膜電晶體主體 層170露出的多晶系矽部份，進行局部氧化反應。經過氧 化反應後，空窗240中曝露出的薄膜電晶體主體層170的厚 度會減少，約從1000A減少爲約250A。局部氧化反應會在 變薄的薄膜電晶體主體層170上（例如變薄的薄膜電晶體之 通道190上），形成一厚的氧化層245。 請參照第9圖，去除氮化物層230，例如利用熱磷酸。 接著，進行毯覆式的P+離子植入，如第9圖中的箭頭250 所示。離子植入所使用的P+離子，例如是使用流量密度約 爲1015cnf2及能量約爲50KeV的高劑量BF2。厚的氧化層245 係做爲一阻障層，以避免P+離子植入薄膜電晶體的通道 190。因此，P+離子250摻入曝露的薄膜電晶體主體層170 中，形成薄膜電晶體的P+汲極區180及P+源極區185。薄膜 電晶體的汲極區180和源極區185係厚的（厚度約爲 1000A)，且汲極區180經由接點155、接點140和驅動器 ---------όII (請先閲讀背面之注意事項再填寫本頁) 訂 σ丨 經濟部中央標準局貝工消费合作社印裝 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ297公釐） 05 98TWF.DOC/Frank/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（丨工） 的汲極116相連接。 由於薄膜電晶體汲極區180和源極區185的厚度較 厚，因此有較小的片電阻値。這就降低了寄生電阻’特別 是減少了第2a、2b圖中所示的內連線電阻不管寄生 內連線電阻値是否減少，爲了使薄膜電晶體的關閉電流保 持在小範圍，形成之薄膜電晶體通道190的厚度是薄的。 因此，薄膜電晶體中寄生內連線電阻的減少並不會降低薄 膜電晶體的效率。 第10圖繪示依照本發明之製造方法所得到同時具有低 關閉電流和低寄生內連線電阻的薄膜電晶體250。薄膜電 晶體250形成在包含有下拉N型金氧半電晶體K的晶圓200 之上，其作法如第2a-3d圖所述。請參照第10圖’去除第 9圖中之遮蔽氧化層220及厚的通道氧化層245，例如使用 氫氟酸進行等向性的（isotropic)濕蝕刻去除。此時’若想 要調整薄膜電晶體的臨限電壓，可進行毯覆式（blanket)通 道離子植入製程。利用傳統的微影製程，定義第三多晶矽 層Π0，形成所想要的圖案。經過上述製程後，可得有預 期形狀的薄膜電晶體，其具有適當形狀的源極和汲極區’ 且可爲薄膜電晶體互連之用。 接著進行後續的製程步驟，例如形成金屬接觸窗。於 後續製程步驟中熱處理步驟可促使植入的雜質從汲極18〇 和源極185橫向擴散至通道190，如此可橫向擴大汲極180 和源極185的區域且減少通道190的長度。 後續的製程也包括了熱回火及沈積形成一預金屬介電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -a 丁 c 05 9 8TWF.DOC/Frank/002 A7 B7 五、發明説明（丨> ) 層（per-metal-dielectic)300。接著定義預金屬介電層 300 ’形成金屬接觸窗開口。在開口中形成金屬接觸窗之 後’在預金屬介電層300和金屬接觸窗上形成金屬導線。 之後形成一保護層，完成所有製程。 依照本發明製程所得的薄膜電晶體250有約小於IpA 的低關閉電流，同時也有低的寄生內連線電阻。低寄生內 連線電阻可避免降低導通電流。因此，薄膜電晶體250有 很大的導通電流/關閉電流比値。這結果是因對薄膜電晶體 通道作部份氧化以減少該通道的厚度，同時形成一厚的氧 化層來當作隨後離子植入時的罩幕所獲致。 經濟部中央標準局員工消費合作社印製 ^^^1 In ·11 In ϋ·— i ^ m ^^1 r/ (請先閱讀背面之注意事項存填寫本頁) 本發明的製程僅需要二個光罩步驟，這和一般製程所 需的光罩步驟相同。因此，依照本發明製程所需的成本和 一般製程所需的成本是相當的。而跟一般的薄膜電晶體所 不同的是，依照本發明所製得的薄膜電晶體有較佳的效 能’也就是說，雖擁有低的寄生內連線電阻，其導通電流/ 關閉電流的比値仍很大。本發明可應用來製造任何需有低 寄生內連線電阻、低關閉電流、高導通電流、高導通電流/ 關閉電流比値以及低等待電源的任何薄膜電晶體，例如一 薄膜電晶體靜態隨機存取記憶體單元。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家梯準（CNS ) A4規格（21〇><297公釐）1T Printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 05 98TWF.DOC / Frank / 002 A7 B7 V. Description of Invention (I 丨) A thin film transistor shielding oxide layer 220 is formed on the thin film, the thickness of which is about 100, for example people. Please refer to FIG. 7, for example, a chemical vapor deposition method is used to cover the silicon nitride layer 230 on the wafer 200 with a thickness of about 1000A, for example. Then a lithography step is performed to make the photoresist layer 235 cover the area outside the thin film transistor channel 190. After etching the area not covered by the photoresist layer 235, the silicon nitride layer 230 and the shielding oxide layer 220 are etched, and a window 240 is formed on the N-type third polysilicon thin film transistor body layer 170. Referring to FIG. 8, the photoresist layer 235 is removed, and then thermal oxidation is performed. The polysilicon portion of the thin film transistor body layer 170 exposed in the vacant window 240 undergoes a local oxidation reaction. After the oxidation reaction, the thickness of the thin-film transistor body layer 170 exposed in the vacant window 240 decreases, from about 1000A to about 250A. The local oxidation reaction will form a thick oxide layer 245 on the thinned thin film transistor body layer 170 (for example, on the thinned thin film transistor channel 190). Referring to FIG. 9, the nitride layer 230 is removed, for example, using hot phosphoric acid. Next, blanket-type P + ion implantation is performed, as indicated by arrow 250 in FIG. 9. The P + ion used for ion implantation is, for example, a high-dose BF2 with a flow density of about 1015 cnf2 and an energy of about 50 KeV. The thick oxide layer 245 serves as a barrier layer to prevent P + ions from implanting into the channel 190 of the thin film transistor. Therefore, P + ions 250 are incorporated into the exposed thin film transistor body layer 170 to form the P + drain region 180 and P + source region 185 of the thin film transistor. The drain region 180 and the source region 185 of the thin film transistor are thick (thickness is about 1000A), and the drain region 180 passes through the contact 155, the contact 140 and the driver --------- II (please Read the precautions on the back first and then fill out this page) Order σ 丨 The printed paper size of the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy uses the Chinese National Standard (CNS) Α4 specification (210Χ297mm) 05 98TWF.DOC / Frank / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. The invention description (Shu Gong) is connected to the Jiji 116. Since the thickness of the drain region 180 and the source region 185 of the thin film transistor is thicker, there is a smaller sheet resistance value. This reduces the parasitic resistance, especially the interconnection resistance shown in Figures 2a and 2b. No matter whether the parasitic interconnection resistance value is reduced or not, in order to keep the off current of the thin film transistor in a small range, the thin film formed The thickness of the transistor channel 190 is thin. Therefore, the reduction of parasitic interconnect resistance in thin film transistors does not reduce the efficiency of thin film transistors. FIG. 10 shows a thin film transistor 250 having both low off current and low parasitic interconnect resistance obtained according to the manufacturing method of the present invention. The thin film transistor 250 is formed on the wafer 200 including the pull-down N-type metal oxide semi-transistor K, as described in FIGS. 2a-3d. Please refer to Fig. 10 'to remove the masking oxide layer 220 and the thick channel oxide layer 245 in Fig. 9 by, for example, isotropic wet etching using hydrofluoric acid. At this time, if you want to adjust the threshold voltage of the thin film transistor, you can carry out the blanket channel ion implantation process. Using the conventional lithography process, the third polysilicon layer is defined to form the desired pattern. After the above process, a thin-film transistor with a predetermined shape can be obtained, which has appropriately shaped source and drain regions and can be used for thin-film transistor interconnection. Then, subsequent processing steps are performed, for example, forming a metal contact window. In the subsequent process steps, the heat treatment step can cause the implanted impurities to diffuse laterally from the drain 180 and the source 185 to the channel 190, which can laterally expand the area of the drain 180 and the source 185 and reduce the length of the channel 190. Subsequent manufacturing processes also include thermal tempering and deposition to form a pre-metal dielectric. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) -a Ding c 05 9 8TWF.DOC / Frank / 002 A7 B7 V. Description of the invention (丨>) Layer (per-metal-dielectic) 300. Next, a pre-metal dielectric layer 300 'is defined to form a metal contact window opening. After the metal contact window is formed in the opening, a metal wire is formed on the pre-metal dielectric layer 300 and the metal contact window. After that, a protective layer is formed to complete all processes. The thin film transistor 250 obtained according to the process of the present invention has a low turn-off current less than about IpA, and also has a low parasitic interconnect resistance. Low parasitic internal wiring resistance can avoid reducing on-current. Therefore, the thin film transistor 250 has a large on-current / off-current ratio. This result is due to partial oxidation of the thin film transistor channel to reduce the thickness of the channel, and at the same time a thick oxide layer is formed as a mask for subsequent ion implantation. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^^^ 1 In · 11 In ϋ · — i ^ m ^^ 1 r / (please read the precautions on the back and fill in this page) The process of the present invention requires only two The photomask step, which is the same as the photomask step required in a general process. Therefore, the cost of the process according to the present invention is comparable to the cost of the general process. What is different from the general thin film transistor is that the thin film transistor made according to the present invention has better performance. That is to say, although it has low parasitic interconnect resistance, its on / off current ratio The value is still very large. The present invention can be applied to manufacture any thin film transistor that requires low parasitic interconnect resistance, low off current, high on current, high on current / off current ratio, and low standby power, such as a thin film transistor static random storage Take the memory unit. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. This paper scale is applicable to China National Standards (CNS) A4 specifications (21〇 < 297mm)