525344 A7 B7 五、發明説明（1 ) I明背景 發明領域 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於前饋放大器，且特別關於其中的前饋訊 號抵消控制迴路，以及利用IF訊號處理之前饋迴路控制 〇 相關技藝說明 在古典的前饋控制系統中，有二種同時發生的獨立控 制功能。第一者係訊號抵消迴路，另一者係變形抵消迴路 。一般而言，二種迴路控制方法都存在。第一方法係訊號 適應的，而第二方法係藉由使用引示或內部產生的訊號之 非直接控制。每一方法均有優點及缺點。適應性方法在所 需的訊號上操作或在訊號的假副訊號上操作。引示系統會 在系統的策略節點處注入內部產生的訊號，當由控制電路 偵測到及無效化或降低至低値時，其會以動路徑（延遲結 構）平衡主動路徑（放大器）的增益及相位響應。這是所 謂的「前饋抵消」且無效化作用會使前饋放大器系統的變 形抵消效果最佳化。 經濟部智慧財產局員工消費合作社印製 在大部份的目前前饋產品中，第一迴路的控制，亦即 ，訊號抵消迴路，係爲適應性的。有些早期設計使用引示 控制，但是，它們會遭受不良抵消及放大器之引示洩漏。 不良抵消及洩漏之原因如下。 典型的引示應用係在放大器的輸入處注入引示訊號。 在前饋訊號抵消迴路中，訊號會分成二路徑，一爲主動（ 放大），一爲被動（延遲）。主動訊號係取樣的及復合的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一~~' 525344 A7 B7 五、發明説明（2) 反相位。由於引示存在於具有相等振幅之二路徑中，所以 ，當二路徑相等時，其會被抵消或無效化。 (請先閱讀背面之注意事項再填寫本頁) 實際的限制係由於引示通過具有非線性之非完美放大 器時，引示及所需的訊號會交互調變。此交互調變阻礙令 人滿意的迴路平衡。訊號抵消迴路的設計目標係將訊號抵 消節點處的功率最小化。出現在引示上的交互調變會阻礙 真正的引示無效達到最佳訊號抵消。另一主要缺點係由於 訊號施加至系統的輸入，所以，引示會與所示的訊號一起 被放大並出現在系統輸出，因而需要窄的頻寬濾波器以移 除此假引示訊號。這會因爲實際的瀘波器結構之有限Q 而造成輸出功率損耗。 經濟部智慧財產局員工消費合作社印製 慮及這些缺點，適應性方法變成最被廣爲用以控制訊 號抵消迴路的方法。適應性方法可採用功率偵測器以偵測 訊號抵消節點處的平均位準。微控制器調整相位或振幅或 複數增益裝置直至訊號抵消節點處的功率最小化爲止。由 於取樣的訊號僅具有振幅資訊而無相位資訊，所以，這有 點爲互動處理。控制器必須產生複數（亦即，實數及虛數 部份）控制訊號，然而，僅有振幅資訊可資利用。控制器 必須藉由嘗試錯誤以調整相位及振幅以產生訊號無效。另 一議論之處係由於真正的訊號會被取樣，所以，最重要的 是取樣週期會比訊號中的任何包絡變化還長。假使取樣週 期接近包絡中的變化週期，則無效演繹法將不能決定較低 的訊號位準是否爲控制器改變或訊號包絡改變的結果，造 成無止境的找尋無效點或可能的迴路振盪。補救之道係減 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 525344 A7 B7 五、發明説明（3) (請先閱讀背面之注意事項再填寫本頁) 緩取樣的時間至包絡中最慢的改變速率的十分之一。但是 ’此限制不利於對諸如載波出現數目或載波功率的快速改 變等快速訊號位準變化之暫態響應。 實施訊號抵消迴路控制之另一受歡迎的方法係笛卡兒 迴路或鎖相迴路方法，由於其會同時感測相位及振幅資訊 ，所以，其會實質地增加響應時間。對複數振幅控制器的 輸出會直接產生且不要求增加的訊號處理。結果係迴路速 度改進10:1至100:1。其它優點包括對訊號位準包絡變化 不靈敏。儘管笛卡兒迴路或鎖相迴路方法具有這些優點， 其仍有限制及缺點。 經濟部智慧財產局員工消費合作社印製 一限制係通常使用訊號二極體作爲相位偵測器以完成 此笛卡兒迴路。已知二極體具有明確的臨界電壓，且在該 電壓之下，輸入改變時，不會有輸出。當諸如上述的二極 體用於訊號抵消迴路中時，會有明確的訊號臨界，在迴路 可以抵消訊號或平衡迴路之前，必須達到此訊號臨界。這 將使得動態範圍受限在低操作位準。可能的解決之道係至 少對迴路的參考輸入使用限制放大器。雖然造成改進的性 能，但是，由於需要相當高的驅動位準以操作二極體，此 方法造成相當高位準的變形結果。這些結果會漏入放大器 系統的高增益部份且不會由變形抵消處理移除。 前饋放大器中寬泛使用之變形抵消迴路控制係應用注 入於主訊號路徑中某處的訊號引示。原理係偵測位於系統 輸出的引示訊號及藉由使用控制電路以實質地無效化或降 低系統輸出中的引示位準。當變形抵消路徑（誤差放大） 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - 525344 A7 B7_ 五、發明説明（4) (請先閲讀背面之注意事項再填寫本頁) 由主放大器延遲路徑平衡時，引示會無效化。假使相位及 振幅響應在校正頻寬上爲平坦時，則當被視爲變形訊號之 引示無效化時，變形成份會以最佳量減少。此間接迴路對 齊方法具有與放大訊號無關以及即使無RF訊號出現期間 迴路仍維持閉合之優點。 最早的迴路控制方法之一係在載波處將連續波（CW) 經濟部智慧財產局員工消費合作社印製 引示注入主路徑。引示接收器（由降頻轉換器、帶通濾波 IF放大器及偵測器）會偵測引示。偵測到的引示會作爲迴 路平衡或無效之指示。簡單的硬體演繹法會藉由增量或減 量增益及相位調整直至引示位準被降至低位準爲止，以調 整誤差迴路的相位及增益。此方法依靠錯誤嘗試，造成加 長的迴路鎖住時間。較晚期的技術會將引示訊號分成可被 直接用於控制增益及相位之正交分量。藉由將訊號分成正 交分量，則控制訊號的方向及振幅會被直接取出而不用計 算或迭代，以致於迴路查詢時間會可觀地減少。至少一技 術係將二獨立的調變訊號正交地施加於引示上。引示接收 器含有代表相位及振幅資訊之二訊號。頻率選取同步偵測 器會恢復相位及振幅資訊以控制迴路。較晚期的技術需要 以RF頻率操作之經過校正的纜線或相位偏移器。 發明槪述 發明藉由使用用於前饋放大器迴路控制之引示方法以 克服很多上述缺點。發明使用CW引示，此CW引示與混 有引示之區域振盪器相偏移。引示接收器由降頻轉換器、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " 525344 A7 B7 五、發明説明（5) (請先閎讀背面之注意事項再填寫本頁) 帶通濾波IF放大器及偵測器組成，其會偵測引示。降頻 轉換器會將引示訊號轉換成頻率等於偏移之IF訊號。IF 訊號含有引示訊號的所有振幅及相位資訊。IF訊號會遭 受數位取樣以恢復將用於迴路控制之相位及振幅資訊。 偵測到的引示會作爲迴路平衡或無效之標示。但是， 由於相當低的IF頻率，此技術允許振幅及相位資訊（或 者是取決於控制系統之I及Q)被數位取樣選取。所造成 的取樣訊號會整合及施加至振幅及相位（或I及Q)控制 器以調整誤差路徑的量値及相位至與主延遲線路徑相同。 發明利用正交方法以分析引示訊號。引示訊號會被分 成可直接用以控制增益及相位之正交分量。藉由將訊號分 成正交分量，控制訊號的方向及振幅會被直接取出而不用 計算或迭代，以致於迴路查詢時間顯著地降低。數位取樣 係用以恢復將被用以控制迴路之相位及振幅資訊。 經濟部智慧財產局員工消費合作社印製 在取樣的訊號與基頻帶訊號之間連續360度調整會允 許時序訊號調整以致於取樣器會取出迴路鎖定所需之適當 的相位及振幅資訊。由於時序或相位對齊處理會在基頻帶 完成，所以，不需要使用手動的、電壓控制RF頻率相位 移位器或纜線長度的修改以完成校正。藉由控制器控制之 下可取得的360度調整，通常可以與纜線長度等無關，即 可完成系統對齊。 在訊號抵消迴路設計中使用能夠在2 GHz以上操作白勺 高頻主動混合器。此種裝置的實施例係摩托羅拉（Mo tor la) 的MCI 3 143D晶片，其使用雙交互耦合差動裝置對。這允 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --* -8 - 525344 A7 _____B7 ___ 五、發明説明（6) 許線性混合及幾乎完全抵消DC漂移。當操作電流隨著溫 度變化而漂移時，二輸出將彼此追蹤。 (請先閱讀背面之注意事項再填寫本頁) 差動抵消會消除主要的DC漂移並使得通常用於接收 器前端之此混合器可以成功地用於前饋設計中的訊號抵消 控制。由於訊號操作位準非常低，所以，產生的任何變形 結果更加容易被控制或被遮蔽。使用此裝置於訊號抵消控 制之優點係其作爲真正的GHz(高頻）線性乘法器。由於此 裝置在處理訊號時實質上未具有要克服的臨界値，所以， 結果在操作的動態範圍上比訊號混合或偵測之二極體方法 改進至少10dB。 此槪述係有助於快速瞭解發明的本質。配合附圖，參 考下述發明的較佳實施例詳述，可更完整地瞭解本發明。 圖式簡述 圖1係根據發明之前饋放大器的方塊圖，顯示訊號抵 消迴路及誤差迴路控制器。 經濟部智慧財產局員工消費合作社印製 圖2係利用使用線性混合器之卡笛兒迴路方法之訊號 抵消迴路的方塊圖。 圖3係方塊圖，顯示誤差迴路控制器。 圖4係方塊圖，強調根據本發明利用之連續波iF引 示訊號之頻譜的方塊圖。 主要元件對照表 10 前饋放大器 本紙張尺度適财關家縣（CNS ) A4規格（210x297公釐)"" ' 525344 A7 B7 五、發明説明（7) 12 單向耦合器 13 延遲線 (請先閱讀背面之注意事項再填寫本頁) 14 複數調變器 15 主放大器 16 單向耦合器 17 第一迴路 19 取樣單向耦合器 20 單向耦合器 21 單向耦合器 22 複數調變器 24 誤差放大器 25 延遲線 26 單向耦合器 27 主放大器輸出 28 單向耦合器 29 誤差迴路控制器 30 單向耦合器 經濟部智慧財產局員工消費合作社印製 31 高頻線性混合器 33 IF取樣器 34 取樣器 35 數位處理器控制器 36 頻率合成器 37 系統介面 38 帶通濾波器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -10- 525344 A7 B7 五、發明説明（8) (請先閱讀背面之注意事項再填寫本頁) 39 單向耦合器 4〇 控制積分器 41 基頻帶產生器 圭實施例之詳i 經濟部智慧財產局員工消費合作社印製 圖1係顯示根據發明之前饋放大器10。如圖1所示 ’ RF輸入訊號11係由單向耦合器12以近乎降低l〇dB取 樣’以致於幾乎所有（接近90% ) RF訊號繼續延著延遲 線13。由單向耦合器12取樣的訊號會被饋送至複數（亦 即’實數及虛數部份）調變器14，在從單向耦合器30注 入引示訊號之後，訊號會在主放大器15放大。至於RF 輸入，其會繼續通過延遲線1 3，在延遲線1 3，其會被單 向耦合益16取樣’在單向親合器16中，其會當作參考標 準被饋送至第一迴路17，第一迴路17此後會被稱爲訊號 抵消迴路。同時，主放大器1 5的輸出會被取樣單向耦合 器19取樣並耦合回至rF輸入以及由單向耦合器2〇扣除（ 經過適當的相位耦合）。來自主放大器的訊號會傾向於抵 消RF輸入11，僅留下變形成份。變形成份會由單向耦合 器21取樣，且取樣的訊號會被饋送至訊號抵消迴路17。 訊號抵消迴路的目的係使主訊號最小化，且其如下述更加 完整說明所述般執行。 基本上爲變形訊號之其餘訊號會傳送經過複數調變器 22並由誤差放大器24放大，然後會由單向親合器26注 射回至主放大器1 5的輸出（由延遲線25延遲）。單向耦合 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 525344 A7 B7 五、發明説明（9) 器26典型上會以降低10dB注入。來自誤差放大器24之 此耦合會在主放大器1 5的輸出中執行誤差校正。 (請先閱讀背面之注意事項再填寫本頁) 在主放大器15的輸出27，單向耦合器28會以幾乎 下降30至40dB之方式，取樣來自主放大器15之誤差減 少的訊號。來自單向親合器2 8之訊號會作爲輸入至誤差 迴路控制器29之引示輸入訊號，誤差迴路控制器29會控 制複數調變器22，以產生會在主放大器的輸入由單向耦 合器30注入之引示輸出訊號。複數調變器22係由誤差迴 路控制器29所控制，以致於使得延遲路徑及誤差路徑相 等且相位差1 80° ，藉以抵消變形產物。 由操作原理相同，所以，複數調變器14及22可爲 IQ調變器，或是它們可爲相位及振幅調整器。 經濟部智慧財產局員工消費合作社印製 圖2係訊號抵消迴路17.的詳細方塊圖。高頻線性混 合器31係用以克服訊號抵消迴路17設計中使用被動混合 器之很多缺點。一此種裝置係摩托羅拉的MCI 3 143D晶片 ，其利用裝置之雙交錯耦合差動對並以2GHz頻率操作。 使用此裝置的優點係取得線性混頻及幾乎完成抵消DC漂 移。當操作電流隨著溫度變化而漂移時，二者將彼此追蹤 。使用此混合器，由於處理訊號時，實質上無須克服臨界 値，所以，其相較於訊號混合或偵測之二極體方法，在操 作的動態範圍上，可以造成至少1 0 (I〇d B)的改進。 圖3係誤差迴路控制區29的詳細方塊圖。CW引示 訊號會注入主放大器1 5鏈。任何漏入誤差路徑或直接進 入引示接收器之引示會造成系統性能變差。引示訊號28 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12- 525344 A7 B7525344 A7 B7 V. Description of the invention (1) Background of the invention (please read the notes on the back before filling out this page) The present invention relates to feedforward amplifiers, and particularly to the feedforward signal cancellation control loops therein, and the use of IF signal processing before feed-forward loop control. Relevant technical description. In a classic feed-forward control system, there are two independent control functions that occur simultaneously. The first is a signal cancellation circuit, and the other is a distortion cancellation circuit. In general, both loop control methods exist. The first method is signal-adaptive, while the second method is indirect control through the use of pilots or internally generated signals. Each method has advantages and disadvantages. The adaptive method operates on the desired signal or on a false secondary signal of the signal. The guidance system will inject internally generated signals at the system's strategy nodes. When detected by the control circuit and invalidated or reduced to a low level, it will balance the gain of the active path (amplifier) with a dynamic path (delay structure) And phase response. This is the so-called "feed-forward cancellation" and the invalidation effect will optimize the deformation cancellation effect of the feed-forward amplifier system. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. In most of the current feedforward products, the control of the first loop, that is, the signal cancellation loop, is adaptive. Some early designs used pilot control, but they suffered from poor cancellation and pilot leakage from the amplifier. The reasons for the poor offset and leakage are as follows. A typical pilot application involves injecting a pilot signal at the input of an amplifier. In the feedforward signal cancellation circuit, the signal is divided into two paths, one is active (amplified) and the other is passive (delayed). Active signals are sampled and composite. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). I ~~ '525344 A7 B7 V. Description of the invention (2) Anti-phase. Since the reference exists in the two paths with equal amplitude, when the two paths are equal, they will be cancelled or invalidated. (Please read the cautions on the back before filling out this page.) The actual limitation is that when the guide passes through a non-perfect amplifier with non-linearity, the guide and the required signal will be modulated interactively. This intermodulation hinders satisfactory circuit balance. The design goal of the signal cancellation loop is to minimize the power at the signal cancellation node. The intermodulation that appears on the pilot prevents true pilots from becoming ineffective to achieve the best signal offset. Another major disadvantage is that the signal is applied to the input of the system, so the pilot will be amplified along with the signal shown and appear at the system output. A narrow bandwidth filter is required to remove this false pilot signal. This will cause the output power loss due to the finite Q of the actual wave filter structure. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In view of these shortcomings, the adaptive method has become the most widely used method to control the signal cancellation loop. The adaptive method can use a power detector to detect the average level of the signal offset node. The microcontroller adjusts the phase or amplitude or complex gain devices until the power at the signal cancellation node is minimized. Since the sampled signal has only amplitude information and no phase information, this is an interactive process. The controller must generate complex (ie, real and imaginary) control signals, however, only amplitude information is available. The controller must adjust the phase and amplitude by trial and error to generate invalid signals. Another argument is that since real signals are sampled, the most important thing is that the sampling period is longer than any envelope change in the signal. If the sampling period is close to the change period in the envelope, the invalid deduction method will not be able to determine whether the lower signal level is the result of a change in the controller or the signal envelope, resulting in endless search for invalid points or possible loop oscillations. The way to remedy is to reduce the paper size to the Chinese National Standard (CNS) A4 specification (210X297 mm) 525344 A7 B7 V. Description of the invention (3) (Please read the precautions on the back before filling this page) Delay the sampling time To the tenth of the slowest rate of change in the envelope. However, 'this limitation is not conducive to transient response to rapid signal level changes such as the number of carrier occurrences or rapid changes in carrier power. Another popular method for implementing signal cancellation loop control is the Cartesian loop or phase-locked loop method, which will substantially increase the response time because it will simultaneously sense the phase and amplitude information. The output of the complex amplitude controller is generated directly and does not require additional signal processing. The result is a loop speed improvement of 10: 1 to 100: 1. Other advantages include insensitivity to signal level envelope changes. Despite the advantages of the Cartesian or phase-locked loop method, there are limitations and disadvantages. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A restriction system usually uses a signal diode as a phase detector to complete this Cartesian circuit. It is known that the diode has a clear threshold voltage, and below this voltage, there will be no output when the input changes. When a diode such as the above is used in a signal cancellation circuit, there is a clear signal threshold. This signal threshold must be reached before the circuit can cancel the signal or balance the circuit. This will limit the dynamic range to low operating levels. A possible solution is to use a limiting amplifier for at least the reference input of the loop. Although resulting in improved performance, this method results in a relatively high level of deformation results because a relatively high drive level is required to operate the diode. These results leak into the high-gain part of the amplifier system and are not removed by the distortion cancellation process. The widely used distortion cancellation loop control in the feedforward amplifier is based on the signal injected somewhere in the main signal path. The principle is to detect the pilot signal located at the system output and to use the control circuit to substantially invalidate or reduce the pilot level in the system output. When the distortion canceling path (enlargement of error) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6-525344 A7 B7_ V. Description of the invention (4) (Please read the precautions on the back before filling this page ) Pilots are invalidated when the delay path is balanced by the main amplifier. If the phase and amplitude responses are flat in the correction bandwidth, the distortion component will be reduced by the optimum amount when the indications that are considered as distortion signals are invalidated. This indirect loop alignment method has the advantages of being independent of the amplified signal and maintaining the loop closed even when no RF signal is present. One of the earliest loop control methods was to inject the continuous wave (CW) printed instructions from the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs into the main path at the carrier. The pilot receiver (by a down-converter, band-pass filtered IF amplifier, and detector) detects the pilot. The detected cue is used as an indication of circuit balance or invalidity. The simple hardware deduction method will adjust the phase and gain of the error loop by increasing or decreasing the gain and phase adjustment until the pilot level is reduced to a low level. This method relies on erroneous attempts, resulting in increased loop lock time. Later techniques split the pilot signal into quadrature components that can be used directly to control gain and phase. By dividing the signal into orthogonal components, the direction and amplitude of the control signal will be taken directly without calculation or iteration, so that the loop query time will be significantly reduced. At least one technology applies two independent modulation signals orthogonally to the pilot. The pilot receiver contains two signals representing phase and amplitude information. The frequency-selective sync detector will recover phase and amplitude information to control the loop. Later technologies required calibrated cables or phase shifters operating at RF frequencies. SUMMARY OF THE INVENTION The invention overcomes many of the above disadvantages by using a pilot method for feedforward amplifier loop control. The invention uses a CW pilot, which is offset from the area oscillator mixed with the pilot. The receiver is indicated by a down-converter, and the paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) " 525344 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before filling (This page) consists of a band-pass filtered IF amplifier and a detector, which detect the pilot. The down-converter converts the pilot signal into an IF signal with a frequency equal to the offset. The IF signal contains all the amplitude and phase information of the pilot signal. The IF signal is digitally sampled to recover the phase and amplitude information that will be used for loop control. The detected cue is used as a sign of circuit balance or ineffectiveness. However, due to the relatively low IF frequency, this technique allows amplitude and phase information (or I and Q depending on the control system) to be selected by digital sampling. The resulting sampling signal is integrated and applied to an amplitude and phase (or I and Q) controller to adjust the magnitude and phase of the error path to be the same as the main delay line path. The invention uses an orthogonal method to analyze the pilot signal. The pilot signal is divided into quadrature components that can be directly used to control gain and phase. By dividing the signal into orthogonal components, the direction and amplitude of the control signal will be taken directly without calculation or iteration, so that the loop query time is significantly reduced. Digital sampling is used to recover the phase and amplitude information that will be used to control the loop. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Continuous 360-degree adjustment between the sampled signal and the baseband signal will allow the timing signal to be adjusted so that the sampler will take out the appropriate phase and amplitude information required for loop lock. Because timing or phase alignment processing is done in the baseband, no manual, voltage-controlled RF frequency phase shifter or cable length modification is required to complete the correction. With the 360-degree adjustments available under the control of the controller, the system alignment can usually be done regardless of cable length, etc. Use a high-frequency active mixer capable of operating above 2 GHz in the signal cancellation loop design. An example of such a device is Motorola's MCI 3 143D wafer, which uses a dual-interaction differential device pair. This allows the paper size to apply Chinese National Standard (CNS) A4 specifications (210X297 mm)-* -8-525344 A7 _____B7 ___ V. Description of the invention (6) Allows linear mixing and almost completely offsets DC drift. When the operating current drifts with temperature, the two outputs will track each other. (Please read the notes on the back before filling out this page.) Differential cancellation will eliminate the main DC drift and make this mixer commonly used in the front end of the receiver can be successfully used for signal cancellation control in feedforward design. Since the signal operation level is very low, any deformation results are more easily controlled or masked. The advantage of using this device for signal cancellation control is that it acts as a true GHz (high frequency) linear multiplier. Since the device does not substantially have a critical threshold to overcome when processing signals, the result is an improvement in the dynamic range of operation of at least 10 dB over the signal mixing or detection diode method. This narrative helps to quickly understand the nature of the invention. With reference to the accompanying drawings, reference will be made to the following detailed description of the preferred embodiments of the invention, so that the invention can be more fully understood. Brief Description of the Drawings Figure 1 is a block diagram of a feedforward amplifier according to the invention, showing a signal cancellation loop and an error loop controller. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative. Figure 2 is a block diagram of the signal cancellation circuit using the Cartier circuit method using a linear mixer. Figure 3 is a block diagram showing the error loop controller. Fig. 4 is a block diagram emphasizing a block diagram of the frequency spectrum of a continuous wave iF pilot signal utilized in accordance with the present invention. Main components comparison table 10 Feed-forward amplifier This paper size is suitable for Guancai County (CNS) A4 size (210x297 mm) " " '525344 A7 B7 V. Description of the invention (7) 12 Unidirectional coupler 13 Delay line ( (Please read the notes on the back before filling in this page) 14 Complex modulator 15 Main amplifier 16 Unidirectional coupler 17 First circuit 19 Sampling unidirectional coupler 20 Unidirectional coupler 21 Unidirectional coupler 22 Complex modulator 24 Error amplifier 25 Delay line 26 One-way coupler 27 Main amplifier output 28 One-way coupler 29 Error loop controller 30 One-way coupler Printed by the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumer Cooperative 31 High-frequency linear mixer 33 IF sampler 34 sampler 35 digital processor controller 36 frequency synthesizer 37 system interface 38 band-pass filter This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) -10- 525344 A7 B7 V. Description of the invention ( 8) (Please read the notes on the back before filling out this page) 39 Unidirectional coupler 40 Control integrator 41 Details of the baseband generator embodiment Printed by FFC Figure 1 shows a feedforward amplifier 10 according to the invention. As shown in FIG. 1, the 'RF input signal 11 is sampled by the unidirectional coupler 12 with a reduction of nearly 10 dB' so that almost all (nearly 90%) RF signals continue along the delay line 13. The signal sampled by the one-way coupler 12 will be fed to the complex (i.e., the 'real and imaginary part') modulator 14. After the pilot signal is injected from the one-way coupler 30, the signal will be amplified at the main amplifier 15. As for the RF input, it will continue to pass through the delay line 13 and at the delay line 13 it will be sampled by the unidirectional coupling 16 'in the one-way coupling 16 it will be fed to the first loop 17 as a reference standard The first circuit 17 will be hereinafter referred to as the signal cancellation circuit. At the same time, the output of the main amplifier 15 is sampled by the sampling unidirectional coupler 19 and coupled back to the rF input and subtracted by the unidirectional coupler 20 (after proper phase coupling). The signal from the main amplifier will tend to cancel the RF input 11, leaving only the distortion component. The distortion component is sampled by the one-way coupler 21, and the sampled signal is fed to the signal cancellation circuit 17. The purpose of the signal cancellation loop is to minimize the main signal and it is performed as described in the more complete description below. Basically, the rest of the deformed signal is transmitted through the complex modulator 22 and amplified by the error amplifier 24, and then injected by the one-way coupler 26 to the output of the main amplifier 15 (delayed by the delay line 25). Unidirectional Coupling This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-525344 A7 B7 V. Description of the invention (9) The device 26 is typically injected at a 10dB reduction. This coupling from the error amplifier 24 performs error correction in the output of the main amplifier 15. (Please read the precautions on the back before filling this page.) At the output 27 of the main amplifier 15, the one-way coupler 28 will drop the signal from the main amplifier 15 with a decrease of almost 30 to 40 dB. The signal from the one-way coupler 28 will be used as a lead input signal to the error loop controller 29. The error loop controller 29 will control the complex modulator 22 to generate a unidirectional coupling at the input of the main amplifier. The pilot output signal injected by the device 30. The complex modulator 22 is controlled by the error circuit controller 29 so that the delay path and the error path are equal and the phase difference is 180 °, thereby cancelling the deformation products. Since the operating principle is the same, the complex modulators 14 and 22 may be IQ modulators, or they may be phase and amplitude regulators. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 2 is a detailed block diagram of the signal cancellation circuit 17. The high-frequency linear mixer 31 is used to overcome many of the disadvantages of using a passive mixer in the design of the signal cancellation circuit 17. One such device is Motorola's MCI 3 143D chip, which utilizes the device's dual interleaved differential pair and operates at a frequency of 2 GHz. The advantages of using this device are linear mixing and almost complete offset of DC drift. When the operating current drifts with temperature, the two will track each other. Using this mixer, since it is not necessary to overcome the critical threshold when processing signals, it can cause at least 1 0 (I0d) in the dynamic range of operation compared to the diode method of signal mixing or detection. B) Improvement. FIG. 3 is a detailed block diagram of the error loop control area 29. The CW pilot signal is injected into the main amplifier 15 chain. Any leakage into the error path or direct entry into the pilot receiver will degrade system performance. Pilot signal 28 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -12- 525344 A7 B7
五、發明説明（A (請先閱讀背面之注意事項再填寫本頁) 因而會於主放大器鏈的中間級處較佳地注入，在此處，引 示較少機會漏入誤差路徑的輸入中。但是，引示也可在主 放器鏈的輸入、輸出、或任何其它級處注入。較佳地，引 示會以低於所示的系統訊號位準30至50dB注入。雖然， 也可使用其它注入位準，但是，太高的位準將造成過多的 引示洩漏，而不足的注入位準會造成不當的迴路控制。 位於誤差放大器24之後的前饋系統輸出的輸出端上 之單向耦合變頻器39會取徵引示及輸出訊號。帶通瀘波 器3 8會衰減輸出訊號以便防止變頻器39過度驅動。較佳 地，輸出訊號會被衰減10或20 dB。由於在正常迴路操 作期間引示會由控制電路減少或無效化幾乎另一 30 dB， 所以，所使用的降頻轉換器會較佳地爲具有寬動態範圍。 IF訊號典型上小於500微伏特，較佳地由相當高增 益低頻（典型上爲100 KHz或更低）之IF放大器33放大 及帶通。對本申請案而言，現貨之雙重運算放大器是令人 滿意的。所需之典型增益接近60dB(1000之電壓增益）。 經濟部智慧財產局員工消費合作社印製 所造成之ID放大器33的輸出訊號會施加至由數位處理器 控制器35控制之二訊號取樣器34。訊號取樣器34較佳 地爲5伏特邏輯位準驅動之CMOS類比開關，但是也可爲 任何其它的類比或數位開關。取樣器34會從IF訊號中取 出振幅及相位或I及Q資訊。取樣的訊號會由控制積分器 40積分，並施加至適當的振幅及相位（或I及Q控制器 )以調整誤差路徑的量値及相位至同於主延遲線路徑35 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） -13 - 525344 A7 B7_ 五、發明説明（彳)| (請先閱讀背面之注意事項再填寫本頁) 數位控制器組件35會產生主參考訊號以由合成器36 、基頻帶產生器41、及取樣開關34使用，也會提供時計 訊號用於微控制器（未顯示）。主參考訊號會向下向成 250 KHz。此250 KHz訊號會被施加至八位元計數器。八 位元輸出會被施加至ROM(唯讀記憶體）。加法器會使計數 偏移6位元（64計數）。此偏移的八位元字會被施加至另一 相同的ROM。此二ROM均含有正弦轉換表之碼。數位對 類比轉換器會輸出二個具有相等振幅及相位偏移90度之 接近ΙΚΗζ的正弦波43。所造成的正弦及餘弦波形43會 被施加至向量調變器41之I及Q輸入。基頻帶訊號43符 合產生本申請案中作爲引示訊號之單側頻帶受抑制載波或 頻率偏移之要求。 經濟部智慧財產局員工消費合作社印製 八位元計數器及偏移的八位元計數器輸出也與四位元 比較器有關。微控制器的輸出埠會控制及設定參考號。微 控制器會設定八位元數目，其會從0-255增量或減量。比 較器的八位元輸出會用以驅動產生用於取樣開關的波形之 雙重正反器。藉由增量此八位元字之參考字，微控制器會 允許在取樣訊號與基頻帶訊號之間連續360度的相位調整 。此相位偏移調整允許微控制器調整時序訊號，以致於取 樣器會取出適當的相位及振幅資訊以鎖住迴路。 一旦正確地決定相位偏移，則八位元偏移數目會儲存 於控制器的非揮發性記憶體中，以在供電啓動時被呼叫。 由於時序或相位對齊處理會於基頻帶完成，所以，其通常 不需使用手動的、電壓控制RF頻率相位位移器或修改纜 本紙張尺度通用中國國家標準（CNS ) A4規格（210X297公釐） -14 - 525344 A7 B7 五、發明説明（4 線長度以完成校正。藉由在微控制器控制下可取得的360 度調整，則與纜線長度等無關之系統的對齊通常是可能的 (請先閱讀背面之注意事項再填寫本頁) 〇 當迴路鎖於引示上時，二訊號取樣器34的額定積分 輸出爲零。出現在這些積分節點之任何顯著的電壓係標示 個別迴路（振幅或相位）未被鎖住。這二個迴路在正常操作 期間維持鎖住，以致於二積分器節點會供予變形抵消迴路 系統的操作狀態。電壓範圍典型上爲+及-5伏特。簡單的 電阻分壓器位準會使此電壓以可由微控制器類比輸入埠直 接讀取的2.50爲中心，使此電壓偏移〇至5伏特。二迴 路狀態輸出會連接至微控制器的類比輸入埠。 在供電啓動時，微控制器的主要功能係傳送引示頻率 資訊給頻率合成器36。假使先前系統已在操作，則相位 偏移資料會被送至加法器。系統具有正常操作直至電源關 閉之所有資訊。 經濟部智慧財產局員工消費合作社印製 微控制器的其它功能係內部系統介面、迴路故障監視 、放大器控制、及自動校正。介面係用以傳輸迴路控制系 統狀態、控制外部手動對齊、或用於一般故障排除。其它 微控制器介面功能係假使控制迴路故障及例行校正時，關 閉其它系統元件。 假使未鎖住條件存在時，微控制器會視那一迴路未鎖 住而採取動作。假使第一迴路（訊號抵消）狀態線之一顯 示未鎖住條件時，則微控制器立即關閉誤差放大器24及 主放大器15。由於第一迴路故障會造成對誤差輸出放大 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 525344 A7 B7 五、發明説明（& (請先閱讀背面之注意事項再填寫本頁) 器24及主輸出放大器1 5危險的過驅動，所以，採取此動 作。在短時間之後，主放大器1 5將被開啓且迴路狀況再 度被檢查。假使其仍然未鎖住，則主放大器1 5會被關閉 。此處理可以被程式化以在放大器被永久地關閉之前循環 預設次數。假使有一變形抵消迴路狀態線顯示未鎖住條件 ，則誤差放大器24會立即被關閉。微處理器在嘗試修正 問題時將嘗試自動校正程序。誤差放大器24會被開啓且 迴路狀態會再度被檢查。假使迴路仍然未被鎖住，則在放 大器24被永久地關閉之前，會如同對第一迴路般，自動 校正程序會重覆數次。 經濟部智慧財產局員工消費合作社印製 在迴路無法鎖住時及製造對齊及測試期間，微控制器 會於供電啓動時，提供以週期爲基礎之自動校正。文字格 式之自動校正指令組將完成下述。在外部命令或狀態訊號 時，微控制器將關閉誤差放大器24。二狀態線將被監視 。微控制器將使相位偏移增量直至相位狀態讀到代表零之 2.50伏特爲止。這是因爲狀態電壓會被偏移，以致於單向 類比對數位轉換器可以讀取狀態訊號的全部動態範圍。同 時，時間振幅狀態線電壓將可觀地升至零以上。由於系統 係被數位地計時，所以，無效値及峰値應發生於相同的偏 移設定。一旦決定此無效値及峰値，微控制器會開啓誤差 放大器24及監視迴路狀態電壓。二電壓均會掉至表示迴 路鎖住條件之零（或2.50伏特）。此處理可較佳地程式化， 以在每次供電啓動時發生，但也可由來自外部訊號之命令 或是由未鎖住（故障）條件促使發生。由於元件老化係迴 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） -16- 525344 A7 B7 五、發明説明（4 路故障的主要原因且迴路故障係前饋放大器故障最常見的 原因’所以，自動校正特徵在系統控制器技藝狀態中係主 要的可靠度進步。 圖4係方塊圖，強調根據較佳實施例所使用的連續波 IF引示訊號之頻譜。 已參考特定說明的實施例，說明發明。應暸解發明不 限於上述實施例且習於此技藝者在不悖離發明的精神及範 圍下可以作不同的改變及修改。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^紙張尺度適用中國國家標準(CNS )八4規格（2獻297公釐） -17-V. Description of the invention (A (please read the notes on the back before filling out this page) Therefore, it will be better injected at the middle stage of the main amplifier chain. Here, it will introduce less chances to leak into the input of the error path. However, the pilot can also be injected at the input, output, or any other stage of the main amplifier chain. Preferably, the pilot will be injected at 30 to 50 dB below the system signal level shown. Although, it is also possible Other injection levels are used, however, too high levels will cause excessive pilot leakage, while insufficient injection levels will cause improper loop control. One-way at the output of the feedforward system output after the error amplifier 24 Coupling the frequency converter 39 will take the indication and output signal. The bandpass wave filter 38 will attenuate the output signal in order to prevent the frequency converter 39 from overdriving. Preferably, the output signal will be attenuated by 10 or 20 dB. During the pilot, the control circuit will reduce or invalidate almost another 30 dB, so the down-converter used will preferably have a wide dynamic range. The IF signal is typically less than 500 microvolts, preferably by When the high-gain low-frequency (typically 100 KHz or lower) IF amplifier 33 is amplified and bandpassed. For the purpose of this application, the dual operational amplifier in the stock is satisfactory. The typical gain required is close to 60dB (1000 Voltage gain). The output signal of the ID amplifier 33 produced by the Intellectual Property Bureau of the Ministry of Economic Affairs ’s consumer cooperative will be applied to the second signal sampler 34 controlled by the digital processor controller 35. The signal sampler 34 is preferably 5 Volt logic level driven CMOS analog switch, but it can also be any other analog or digital switch. The sampler 34 will take the amplitude and phase or I and Q information from the IF signal. The sampled signal will be integrated by the control integrator 40 , And apply to the appropriate amplitude and phase (or I and Q controllers) to adjust the magnitude and phase of the error path to the same as the main delay line path. 35 This paper size applies the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) -13-525344 A7 B7_ V. Description of the invention (彳) | (Please read the precautions on the back before filling this page) The digital controller component 35 will generate a main reference signal for cooperation. The generator 36, the baseband generator 41, and the sampling switch 34 are also used to provide a timepiece signal for a microcontroller (not shown). The main reference signal will go down to 250 KHz. This 250 KHz signal will be applied to 8-bit counter. The 8-bit output is applied to ROM (read-only memory). The adder shifts the count by 6 bits (64 counts). This offset octet word is applied to another The same ROM. Both ROMs contain the codes of the sine conversion table. The digital analog converter will output two sine waves close to IK 及 ζ with equal amplitude and phase shift of 90 degrees. The resulting sine and cosine waveforms 43 will The I and Q inputs are applied to the vector modulator 41. The baseband signal 43 meets the requirements for the suppressed carrier or frequency offset of the single-sided frequency band used as the pilot signal in this application. The eight-bit counter and offset eight-bit counter output printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are also related to the four-bit comparator. The output port of the microcontroller will control and set the reference number. The microcontroller will set the number of octets, which will increase or decrease from 0-255. The eight-bit output of the comparator is used to drive a dual flip-flop that generates a waveform for the sampling switch. By incrementing the reference word of this octet, the microcontroller will allow a continuous 360-degree phase adjustment between the sampled signal and the baseband signal. This phase offset adjustment allows the microcontroller to adjust the timing signal so that the sampler will take the appropriate phase and amplitude information to lock the loop. Once the phase offset is correctly determined, the number of octets is stored in the controller's non-volatile memory to be called when power is turned on. Because the timing or phase alignment processing is done in the baseband, it usually does not require the use of a manual, voltage-controlled RF frequency phase shifter or modification of the cable. The paper size is generally the Chinese National Standard (CNS) A4 specification (210X297 mm)- 14-525344 A7 B7 V. Description of the invention (4-wire length to complete the correction. With 360-degree adjustments available under the control of a microcontroller, alignment of systems unrelated to cable length etc. is usually possible (please first Read the notes on the back and fill in this page again.) 〇 When the loop is locked on the guide, the rated integral output of the two-signal sampler 34 is zero. Any significant voltage appearing at these integration nodes indicates the individual loop (amplitude or phase). ) Unlocked. These two loops remain locked during normal operation, so that the two integrator nodes will supply the operating state of the distortion cancellation loop system. The voltage range is typically + and -5 volts. Simple resistance points The voltage level of the voltage will center this voltage at 2.50 which can be read directly by the analog input port of the microcontroller, shifting this voltage by 0 to 5 volts. Second circuit status output It will be connected to the analog input port of the microcontroller. When the power is turned on, the main function of the microcontroller is to send the pilot frequency information to the frequency synthesizer 36. If the previous system is already operating, the phase offset data will be sent to Adder. The system has all the information from normal operation until the power is turned off. The other functions of the microcontroller printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are the internal system interface, loop fault monitoring, amplifier control, and automatic calibration. The interface is used for The transmission loop controls system status, controls external manual alignment, or is used for general troubleshooting. Other microcontroller interface functions are to shut down other system components during control loop failures and routine corrections. If an unlocked condition exists, the micro-controller The controller will act as if that circuit is not locked. If one of the status lines of the first circuit (signal cancellation) shows an unlocked condition, the microcontroller immediately turns off the error amplifier 24 and the main amplifier 15. Because the first circuit Failure will cause amplification of error output. The paper size applies Chinese National Standard (CNS) A 4 Specifications (210X297 mm) -15- 525344 A7 B7 V. Description of the invention (& Please read the notes on the back before filling this page) Device 24 and main output amplifier 1 5 Dangerous overdrive, so take this Action. After a short time, the main amplifier 15 will be turned on and the loop condition will be checked again. If it is still unlocked, the main amplifier 15 will be turned off. This process can be programmed to permanently turn off the amplifier Preset the number of times before. If there is a deformed offset circuit status line showing an unlocked condition, the error amplifier 24 will be turned off immediately. The microprocessor will try to automatically correct the program when trying to correct the problem. The error amplifier 24 is turned on and the circuit The condition will be checked again. If the loop is still unlocked, the automatic calibration procedure will be repeated several times as for the first loop before the amplifier 24 is permanently turned off. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the loop cannot be locked and during manufacturing alignment and testing, the microcontroller will provide cycle-based automatic calibration when the power is turned on. The text format of the automatic correction command group will complete the following. Upon an external command or status signal, the microcontroller will turn off the error amplifier 24. Two status lines will be monitored. The microcontroller will increment the phase offset until the phase state reads to 2.50 volts representing zero. This is because the state voltage is shifted so that the unidirectional analog-to-digital converter can read the full dynamic range of the state signal. At the same time, the time-amplitude state line voltage will rise considerably above zero. Since the system is clocked digitally, invalidation and peaking should occur at the same offset setting. Once this ineffectiveness and peak value are determined, the microcontroller turns on the error amplifier 24 and monitors the loop state voltage. Both voltages will drop to zero (or 2.50 volts) indicating the circuit's locked condition. This process can be better programmed to occur each time the power is turned on, but can also be caused by a command from an external signal or by an unlocked (fault) condition. Due to the aging of components, the paper size applies to the Chinese National Standard (CNS) A4 specification (210X29? Mm) -16- 525344 A7 B7 V. Description of the invention (the main reason for 4-channel failure and the loop failure is the most common feed-forward amplifier failure The reason 'So, the automatic correction feature is the main reliability improvement in the state of the system controller technology. Figure 4 is a block diagram that emphasizes the spectrum of the continuous wave IF pilot signal used according to the preferred embodiment. Reference has been made to the specific description The embodiment of the invention illustrates the invention. It should be understood that the invention is not limited to the above embodiments and those skilled in the art can make different changes and modifications without departing from the spirit and scope of the invention. (Please read the precautions on the back before filling out this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ The paper size is applicable to China National Standard (CNS) 8-4 specifications (2 297 mm) -17-