1296840 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶接合方法，特別係有關於一 種使用非導電膠之覆晶接合方法。 【先前技術】 隨著電子產品正走向輕薄短小、1/0數增加及功能提 升之發展趨勢，利用覆晶封裝技術以使電子產品能具有電 齡性傳導佳、尺寸小、散熱佳及高密度等優點，但由於晶片 之凸塊與基板之接點係為表面接觸，且因晶片與基板之應 力不同’因此會有基板翹曲而造成斷路之情形發生。 請參閱第1及2圖，一種習知使用非導電膠之覆晶接 合方法，首先’如第1圖所示，提供一基板丨丨〇，該基板 110之一上表面111係形成有複數個接點〗丨2，該基板u 〇 係可為一種可撓性基板。之後，點塗形成一非導電膠12 〇 於該些接點112上。接著，提供一晶片j 3 〇，該晶片13 〇 > 之一主動面13 1上係設置有複數個金凸塊丨32，並以熱壓 合方式使該晶片130之該些金凸塊132通過該非導電膠 120’且該晶片130之該些金凸塊132對準該基板11〇之 該些接點112。之後，如第2圖所示，經熱壓合步驟後， 該些凸塊132係電性接觸至該些接點丨12，然而由於該些 金凸塊132與該些接點112係為表面接觸，因此容易受熱 應力效應而發生斷路，其導電可靠度不佳。 【發明内容】 本發明之主要目的係在於提供一種使用非導電膠之 6 12968401296840 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a flip chip bonding method, and more particularly to a flip chip bonding method using a non-conductive paste. [Prior Art] With the trend of thinner and lighter, 1/0 increase and functional improvement, the use of flip chip packaging technology enables electronic products to have good electrical conductivity, small size, good heat dissipation and high density. The advantage is that, since the bump of the wafer and the substrate are in surface contact, and the stress between the wafer and the substrate is different, the substrate is warped and the circuit is broken. Referring to FIGS. 1 and 2, a conventional method of flip chip bonding using a non-conductive paste, first, as shown in FIG. 1, a substrate is provided, and an upper surface 111 of the substrate 110 is formed with a plurality of layers. Contact 丨 2, the substrate u can be a flexible substrate. Thereafter, a non-conductive paste 12 is formed by spot coating on the contacts 112. Next, a wafer j 3 〇 is provided. The active surface 13 1 of the wafer 13 〇 is provided with a plurality of gold bumps 32, and the gold bumps 132 of the wafer 130 are thermally pressed. The gold bumps 132 of the wafer 130 are aligned with the contacts 112 of the substrate 11 through the non-conductive paste 120'. Then, as shown in FIG. 2, after the thermal pressing step, the bumps 132 are electrically connected to the contacts 12, but the gold bumps 132 and the contacts 112 are surfaced. Contact, so it is easy to be broken by thermal stress effect, and its conduction reliability is not good. SUMMARY OF THE INVENTION The main object of the present invention is to provide a non-conductive adhesive 6 1296840
覆晶接合方法，一模板之一容置穴係放置有複數個導電顆 粒，藉由一刮刀使該些導電顆粒平整排列於該模板之該容 置穴中，下壓_晶片至該模板之該容置穴，並使該晶片之 複數個金凸塊之複數個嵌合表面上沾附該些導電顆粒，該 些金凸塊係通過一非導電膠並藉由該些導電顆粒而電性 連接至一基板之複數個接點，且該些導電顆粒係嵌入該些 凸塊與該些接點，以提升導電可靠度。 本發明之次一目的係在於提供一種使用非導電膠之 覆晶接合方法，其中該些導電顆粒厚度係不大於該些金凸 塊之厚度，可冑免該料電顆粒沾附於該些金凸塊之複數 個側面而造成短路。 依據本發明，一種使用非導電膠之覆晶接合方法，首 先提供一模板，該模板係具有一容置穴，該容置穴係放置 有複數個導電顆粒，提供n藉由移動該刮刀使該些 導電顆粒平整排列於該模板之該容置穴，接著，下壓一具 有複數個金凸塊之晶片至該模板之該容置穴，並使該晶片 之該些金凸塊之一嵌合表面沾附有該些導電顆粒，提供一 土板該基板之表面係具有複數個接點且一非導電膠係 形成於該些接點上，最後，熱壓合該晶片至該非導電膠， 該些金凸塊係通過該非導電膠並藉由該些導電顆粒而電 性連接至該基板之該些接點。 【實施方式】 本發明之具體實施例係揭示一種使用非導電膠之 覆晶接合方法，首先，請參閱第3A圖，提供一模板21〇， 7 1296840 該模板2 1 0係具有一容置穴211，在該容置穴211中並放 置有複數個導電顆粒220，該些導電顆粒22〇係可為不規 則狀且該些導電顆粒2 2 0係不規格排列於該容置穴211。 接著，請參閱第3Β圖，提供一刮刀230，藉由移動該刮刀 230使该些導電顆粒220平整排列於該模板21 〇之該容置 八211’該些導電顆粒220厚度係介於1〇〜4〇微米。之後， 請參閱第3C圖，下壓一晶片240至該模板210之該容置 穴211中，該晶片240係具有複數個金凸塊241，每一金 凸塊241係具有一嵌合表面242及複數個侧面243，其中 該些金凸塊241之該些嵌合表面242係接觸該些導電顆粒 220，並使該些嵌合表面242上沾附有該些導電顆粒22〇， 較佳地，該些導電顆粒220厚度係不大於該些金凸塊241 之厚度，以避免該些導電顆粒220沾附於該些金凸塊241 之該些側面243而造成該晶片240短路，其中該些金凸塊 241之厚度係約為50微米。接著，請參閱第3d圖，提供 一基板250，該基板250係選可自於可撓性電路基板、玻 璃基板、硬質印刷電路板與陶瓷基板之其中之一。該基板 250之一上表面251係形成有複數個接點252且一非導電 膠 260(N〇n_C〇ndiiCtiVe Paste, NCP)係形成於該些接點 252 上，之後，將該晶片240熱壓合至該非導電膠260上。最 後’請參閱第3E圖，經熱壓合步驟後，該些金凸塊24 i 係通過該非導電膠260並藉由該些導電顆粒22〇而電性連 接至該些接點252，較佳地，該些導電顆粒22〇係具有可 刺入該些金凸塊241之尖銳角，使該些導電顆粒220係嵌 8 1296840 入該些金凸塊241之該些嵌合表面242及該基板25〇之該 些接點252,確保該些金凸塊241電性連接至該些接點 252’以提升導電可靠度。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第 1 圖：習知使用非導電膠之覆晶接合製程中晶片 於熱壓合步驟前之截面示意圖。 第 2 圖：習知使用非導電膠之覆晶接合製程中晶片 於熱壓合步驟後之截面示意圖。 第3 A至3 E圖：依據本發明之一具體實施例，一種使用非 導電膠之覆晶接合製程之截面示意圖。 【主要元件符號說明】 110 基板 111 上表面 112 接點 120 非導電膠 130 晶片 131 主動面 132 凸塊 210 模板 211 容置穴 220 導電顆粒 230 刮刀 240 晶片 241 金凸塊 242 嵌合表面 243 侧面 250 基板 251 上表面 252 接點 260 非導電膠In the flip chip bonding method, one of the templates is provided with a plurality of conductive particles, and the conductive particles are evenly arranged in the receiving hole of the template by a doctor blade, and the wafer is pressed to the template. Receiving a hole, and adhering the conductive particles to a plurality of fitting surfaces of the plurality of gold bumps of the wafer, the gold bumps being electrically connected by a non-conductive glue and by the conductive particles a plurality of contacts to a substrate, and the conductive particles are embedded in the bumps and the contacts to improve the reliability of the conductive. A second object of the present invention is to provide a flip chip bonding method using a non-conductive paste, wherein the thickness of the conductive particles is not greater than the thickness of the gold bumps, and the electric particles of the material are adhered to the gold. A plurality of sides of the bump cause a short circuit. According to the present invention, a flip chip bonding method using a non-conductive paste, firstly providing a template having a receiving cavity, the receiving cavity is provided with a plurality of conductive particles, and n is provided by moving the scraper The conductive particles are evenly arranged in the receiving hole of the template, and then pressing a wafer having a plurality of gold bumps to the receiving hole of the template, and fitting one of the gold bumps of the chip The surface is adhered with the conductive particles to provide a soil plate. The surface of the substrate has a plurality of contacts and a non-conductive adhesive is formed on the contacts. Finally, the wafer is thermally pressed to the non-conductive adhesive. The gold bumps are electrically connected to the contacts of the substrate through the non-conductive glue and by the conductive particles. [Embodiment] A specific embodiment of the present invention discloses a flip chip bonding method using a non-conductive paste. First, please refer to FIG. 3A to provide a template 21〇, 7 1296840. The template 2 1 0 system has a receiving hole. 211, a plurality of conductive particles 220 are disposed in the receiving hole 211, and the conductive particles 22 are irregular and the conductive particles are arranged in the receiving hole 211. Next, referring to FIG. 3, a scraper 230 is provided. The conductive particles 220 are evenly arranged on the template 21 by moving the scraper 230. The conductive particles 220 have a thickness of 1〇. ~ 4 〇 micron. Then, referring to FIG. 3C, a wafer 240 is pressed into the receiving hole 211 of the template 210. The wafer 240 has a plurality of gold bumps 241, each of which has a fitting surface 242. And the plurality of side surfaces 243, wherein the plurality of the surface 242 of the gold bumps 241 are in contact with the conductive particles 220, and the conductive surfaces 22 are adhered to the surface 242, preferably The thickness of the conductive particles 220 is not greater than the thickness of the gold bumps 241 to prevent the conductive particles 220 from adhering to the side surfaces 243 of the gold bumps 241 to cause the wafers 240 to be short-circuited. The gold bumps 241 are approximately 50 microns thick. Next, referring to Fig. 3d, a substrate 250 is provided which is selected from one of a flexible circuit substrate, a glass substrate, a hard printed circuit board and a ceramic substrate. An upper surface 251 of the substrate 250 is formed with a plurality of contacts 252, and a non-conductive paste 260 (N〇n_C〇ndiiCtiVe Paste, NCP) is formed on the contacts 252, and then the wafer 240 is hot pressed. The non-conductive adhesive 260 is bonded to the non-conductive adhesive 260. Finally, please refer to FIG. 3E. After the thermocompression bonding step, the gold bumps 24 i are electrically connected to the contacts 252 through the non-conductive paste 260 and electrically connected to the contacts 252. The conductive particles 22 have a sharp angle that can penetrate the gold bumps 241, so that the conductive particles 220 are embedded in the mounting surface 242 of the gold bumps 241 and the substrate. The contacts 252 of 25 , ensure that the gold bumps 241 are electrically connected to the contacts 252 ′ to improve the conductivity reliability. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a wafer before a thermocompression bonding step in a flip chip bonding process using a non-conductive paste. Fig. 2 is a schematic cross-sectional view showing a wafer after a thermocompression bonding step in a flip chip bonding process using a non-conductive paste. 3A to 3E are schematic cross-sectional views showing a flip chip bonding process using a non-conductive paste in accordance with an embodiment of the present invention. [Main component symbol description] 110 substrate 111 upper surface 112 contact 120 non-conductive adhesive 130 wafer 131 active surface 132 bump 210 template 211 receiving hole 220 conductive particles 230 blade 240 wafer 241 gold bump 242 fitting surface 243 side 250 Substrate 251 upper surface 252 contact 260 non-conductive adhesive