WO1981002488A1

WO1981002488A1 - Drive circuit for driving a gas-discharge device

Info

Publication number: WO1981002488A1
Application number: PCT/US1981/000235
Authority: WO
Inventors: L Eichman; J Hardway
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1980-02-27
Filing date: 1981-02-26
Publication date: 1981-09-03
Anticipated expiration: 1982-08-27
Also published as: CA1155572A; EP0046794A4; EP0046794A1; US4347509A; JPS57500210A

Abstract

A circuit for driving a gas-discharge device wherein discharge cells (120) each have a column electrode (28) and a segment electrode (26), includes a transformer (80) whose secondary winding (86) provides operating voltages for application to the electrodes. In operation, the secondary winding (86) is arranged during first time intervals to supply to the column electrodes (28) a first potential while a reference potential is applied to the segment electrodes (26). During second time intervals, the secondary winding (86) is arranged to supply to selected segment electrodes (26) a second potential, the reference potential being applied to selected column electrodes (28). Cells including selected column and segment electrodes are repeatedly ignited. A voltage regulator circuit (196) is coupled to the secondary winding (86).

Description

DRI Ε CIRCUIT FOR DRIVING A GAS-DISCHARGE DEVICE

Technical Field

This invention relates to drive circuits of the kind for driving a gas-discharge device having an array of capaciti ely-coupled cells in which each cell has a column electrode and a segment electrode, said column electrodes being connected by a plurality of column conductors and said segment electrodes being connected by a plurality of segment conductors, including a transformer having primary winding means and secondary winding means.

Background Art

It is known that-a gas discharge cell can be produced in an ionizable gas interposed between first and second electrodes and that, upon the application of a suitable electric potential between the first and second electrodes, the cell will become luminescent because of the ionization which occurs within the cell. This characteristic lends itself quite readily for use in a display panel. A control circuit for driving such display is shown in U.S. Patent No. 3,614,769.

As disclosed in U.S. Patent No. 3,614,769, the application of an electric field to a gas discharge cell causes ionization to occur within the cell. The electric field imparts energy to electrons which collide with other atoms, thus releasing other electrons. This elec¬ tron multiplication process continues until breakdown occurs, at which time ignition occurs, that is, a gaseous discharge occurs within the cell, causing-_^positive charges to be deposited on the cell walls connected to the cath¬ ode and electrons to be deposited on the cell walls con¬ nected to the anode. The charges deposited on the cell walls are trapped because of the capacitive coupling effect exerted by the cell walls. Since positive ions are attached to the cathode wall and electrons are attached to the anode wall, the wall charge will be of_. a polarity opposite to that of the electric field which instigated the gas discharge. In other words, the voltage contributed by the wall charge will be opposite in polarity to the applied electric field. Thus, it can be seen that after discharge occurs, the total voltage impressed on the cell will be the algebraic sums of the voltages applied to the cell terminals plus the voltage contributed by the wall charge, which after ignition is negative with respect to the applied voltage, therefore resulting in a decreased cell voltage.

The gas discharge which occurs in the cell continues until the wall voltage builds up to a certain value. This value is given by the relationship V - V„ < V , where V, is the applied voltage, V_w is the wall voltage, and V is the voltage below which the cell is extinguished. In order to energize the cell again using the same magnitude of applied voltages, it is necessary to reverse the polarity of the applied voltages to the cell, thereby impressing an applied voltage across the cell which is adequate with the wall voltage left from the previous discharge, thus permitting a gas discharge to occur in the reverse direction. Since the wall charge is trapped within the cell, the wall voltage will always oppose the voltage which initiated the gas dis¬ charge.

Information is visually displayed in the display device in the form of characters, the characters being formed by a group of electroluminescent cells or segments containing an encapsulated gas. The illumina¬ tion is provided by a gaseous discharge^"* within the cell which occurs upon the application of an electric field at the cell terminals, thereby igniting the cells. Control circuits are provided for selectively energizing the electroluminescent cells, each of which is capaci- tively coupled between two electrodes, such as a segment electrode and a column electrode. The number of segment electrodes is determined by the number of cells per character, and the number of column electrodes is deter¬ mined by the number of characters in the display device. Electrically, this takes the form of a matrix in which the columns include the column electrodes. Each indi¬ vidual cell is called a segment cell, and the segment cells in each row are connected together. One end of each segment electrode row and each column is connected to a potential source through appropriate drive trans¬ istors. The other ends of the segment rows and the columns are each connected to ground through individual drive transistors. The energization of selected segment cells in addition to the energization of a particular column electrode determines the character to be dis¬ played. Circuit means are provided for logically con¬ trolling the drive transistors.

In order to illuminate a selected cell for display purposes, it is necessary to alternately ener- gize the electrodes connected to the selected cells. In a multiplexing operation of each character, the column electrodes in each of the characters is connected to a common driver together with a selected number of segment cells connected to a common segment driver. During a multiplexing operation, the display's control logic uses both the common column and segment drivers to designate which cells are to be energized. This operation occurs on a scanned "one column at a time" basis. A blanking period is required between the selection of the columns to enable the segment data to be transmitted to the control logic. Because of the large voltages involved to drive such displays, circuits supplying, these high voltage pulses are required which have been very costly thereby increasing the cost of the displays.

Disclosure of the Invention

According to the present invention, there is provided a drive circuit of the kind specified, charac¬ terized in that said secondary winding means is arranged during first time intervals to supply to said column conductors a first potential; while a reference potential is applied to said segment conductor, said secondary winding means being further arranged during second time intervals occurring alternately with said first time intervals, to supply to selected segment conductors a second potential, said reference potential being applied to selected column conductors, whereby cells at the intersection of selected column and segment conductors are repeatedly ignited.

As compared with the system of the aforemen¬ tioned U.S. Patent, the present system has the advantage of lower cost since lower cost, lower voltage transis¬ tors can be employed. Furthermore, a minimum number of circuit elements can be utilized in the present system.

A drive circuit of the kind specified is known from U.S. Patent No. 4,110,663 wherein cells are defined by opposed first and second opposed electrodes. A selected set of first electrodes is supplied with a full bipolar pulse wave, the other sets of first electrodes being supplied with only a prescribed polarity component of the pulse wave. Furthermore, the second electrodes are selectively supplied with a predetermined voltage and the reference voltage. It will be appreciated that such known system differs from the present system wherein the column conductors are supplied with a first potential and have the reference potential selectively coupled thereto.

Brief Description of the Drawings -

Fig. 1 is a sectional view of a gas-discharge cell that can be utilized with the present invention; Fig. 2 is a plan view of a representative character display;

Fig. 3 is a schematicι diagram of a represen¬ tative gas display cell; Fig. 4 is a schematic diagram of the gas- discharge display drive circuit of the present invention;

Figs. 5A-5C inclusive taken together are a schematic diagram of the converter drive portion of the display driver circuits for energizing a cell in accord¬ ance with the present invention;

Fig. 6 is a diagram showing the manner in which Figs. 5A-5C inclusive are arranged with respect to each other to form the driver circuits; Figs. 7A and 7B inclusive taken together are a schematic diagram of the high voltage drive portion of the display driver circuits for energizing a cell in accordance with the present invention;

Fig. ά is a diagram showing the manner in which Figs. 7A and 7B inclusive are arranged with respect to each other to form the driver circuit;

Fig. 9 shows a plurality of waveforms used in the operation of the circuits shown in Figs. 5A-5C inclusive and Figs. 7A and 7B inclusive; and Fig. 10 is a schematic diagram of the oscil¬ lator circuit employed in the driver circuits of the present invention.

Description of the Preferred Embodiment

Fig. 1 is a representation of a gas discharge display cell which may be used with the present inven¬ tion. The cell generally indicated by the numeral 20 usually comprises a glass sandwich.24 encapsulating a gas at a particular pressure. A discharge which occurs in the encapsulated gas and provides sufficient illumina- tion for use in visual displays will occur within the cell 20 upon the application of a particular potential

Va between the electrodes 26 and 28, the electrodes being located externally of the cell in order to utilize its capacitive properties. The electrons and ions created by the discharge will attach to the anode and cathode sides of the glass cell, respectively, to produce what is commonly referred to as a wall charge. The voltage V„ attributed to the wall charge has a polarity opposite to that of the applied voltage Vcl which initiated a discharge. Upon reversal of the applied voltage V , the voltages V and V_w will be additive, thereby causing another discharge to occur and permitting the use of a voltage Vl which can be at a lower level than that which originally initiated a discharge.

Fig. 2 shows a plurality of cells of the type illustrated in Fig. 1 combined to form a conventional 7- bar code matrix 30 comprising seven individual segments or cells 32a-32g inclusive. Individual ones of these segments can be selectively energized to form desired numerical characters. A similar matrix of fourteen individual segments are arranged in a manner that is well-known in the art to form characters of the alpha code.

The cell 20 of Fig. 1 is diagrammatically illustrated in Fig. 3 as being capacitively coupled to the cell electrodes 26 and 28, in which at least one of the electrodes is transparent for the passage of light. Although two coupling capacitances 34 and 36 are illus¬ trated because of the glass dielectric between each exterior electrode and the adjacent interior glass wall surface, one of such coupling capacitors could be eliminated and the combination would still be referred to as a capacitively coupled cell.

The cell electrode 26 (Fig. 3) representing one of the segments 32a-32g inclusive (Fig. 2) is coupled to the emitter 38 of an NPN transistor 40 and the col¬ lector 42 of an NPN transistor 44. The cell electrode 28 representing a column electrode is couRled over a column conductor 176 to a 170 volt A.C. voltage source 60 and the collector 50 of an NPN transistor 52. The collector 54 of the transistor 40 is connected over a segment conductor 100 to a voltage source 56 of 85 volts D.C. The emitters 62 and 64 of the transistors 52 and 44 respectively are connected to ground. The base 76 of transistor 52 connects with driver circuits 68 while the base 70 of transistor 44 is connected with driver circuits 72. As will be explained in more detail hereinafter, the transistor 44 is switched to a conducting state by signals transmitted from the driver circuits 72, thereby impressing 170 volts across the cell electrodes 26 and 28. This 170 volts value is less than the ignition voltage necessary to ignite the cell 20, such ignition voltage being somewhere between 200 and 260 volts. Thus the cell 20 is effective as a capacitor but the cell does not ignite at this time. After the voltage appearing at the electrode 28 has risen to a level of 170 volts, the 170 volts supply is terminated and the transistor 44 is switched into a non- conducting state by the driver signals received from the driver circuits 72 and the transistors 40 and 52 are driven into a conducting state by signals transmitted from the driver circuits 68 and 72. This switching action results in a connection to ground through the transistor 52 and 85 volts being impressed on the elec¬ trode 26 of the selected cells 20 by means of a current path which extends from the emitter-collector path of the transistor 40, through the cell 20 with the coupling capacitors 34 and 36 and through the collector-emitter path of the conducting transistor 52 to ground.

The impressing of the 85 volts on the selected segment electrode 26 (Fig. 3) . combined with the 170 volts potential resulting from the capacitive action of the cell 20 in a manner that is well-known in the art results in the cell 20 reaching a voltage level at which a gaseous discharge occurs. The igniting of the cell 20 and the subsequent discharge causes a wall, charge to be deposited on the inside glass surface walls of the cell 20. The wall charge produces a wall voltage opposite in polarity to that of the applied voltage which initially drove the cell 20 into ignition. Assuming, for purposes of illustration, that the wa__,l charge in the cell 20 contributes a voltage of 170 volts, it is seen that the cell voltage drops to 170 volts after ignition, since the wall voltage V is negative with respect to the applied voltage Va. The transistors 40 and 52 are subsequently switched back into a conductive state to again impress 85 volts at the electrode 26. Upon this occurrence, the voltage across the cell 20 is again sufficiently high to drive the cell into ignition. The above operation is repeated so long as the transistors 40 and 52, together with the transistor 44 are alter¬ nately pulsed into conduction. The present invention provides a high voltage supply for the transistors 40, 44, and 52 by providing a flyback transformer which supplies the 85 and 170 volts required to fire the cell 20 at a high frequency rate which is equal to the system clock in a manner to be described more fully herein¬ after.

Referring now to Fig. 4, there is shown a schematic diagram of the gas discharge display drive circuit of the present invention which includes a flyback transformer generally indicated by the numeral 80 and which includes primary windings 82 coupled to the system power supply 84 and secondary windings 86 which are tapped over line 88 to output 170 volts AC through diode 90 to the column electrodes 28 (Fig. 3) in the gas- discharge display panel 92, over line 94 to output 170 volts DC through diodes 96 and 98 and over line 100 to output 85 volts DC through diodes 102 and 104, the 85 and 170 DC voltage pulses being transmitted to the panel drive circuit 106 which selectively supplies the 85 volt pulses to the segment electrodes 26 (Fig. 3) over bus 108 comprising the segment electrode conductors in accord¬ ance with the data signals transmitted over bus 110 from a data generator 112. The secondary windings 86 of the transformer 80 are also coupled over line 114 to a high voltage converter drive circuit 116 which is driven by timing signals transmitted frpm the panel drive circuitry 106 over line 118. The high voltage con¬ verter drive circuitry 116 controls the operation of the transformer 80 to enable the secondary windings 86 to supply the required voltage pulses to the display panel 92 and the panel drive circuitry 106 in a manner that will be described more fully hereinafter.

Referring now to Figs. 5A-5C inclusive arranged in the manner shown in Fig. 6, there is disclosed the drive circuits for the column electrodes 28 (Fig. 3) in the gas-discharge panel 92. Included in the circuit is a dual flip-flop 120 (Fig. 5A) which over lines llOe and llOf receives appropriate clock signals from the data and clock generator 112 (Fig. 4) and the system oscil¬ lator 135 (Fig. 10) over line 118. The flip-flop 120 is commercially available from the Motorola Semiconductor Products Inc. of Phoenix, Arizona as part no. 74LS74. Unless otherwise stated, all I.C. elements designated hereinafter are commercially available from the Motorola Semiconductor Products Inc. The flip-flop 120 will output over line 122 a blanking pulse to a 74LS42 decoder 124 (Fig. 5B), an inverted blanking pulse over line 126 to one input of a NAND gate 128 and a clocking pulse 130 (Fig. 9b) over line 132 which has a rate of one-half the frequency of the clock pulses 134 (Fig. 9a) received from the system oscillator 135 (Fig. 10) over line 118. The clock pulses 130 appearing on line 132 are inputted into a 74LS42 decoder 136 which also receives over line 118 the clock pulses 134 (Fig. 9a) from the system oscillator 135 (Fig. 10) and which are generated at a rate of 85

KHz. in a manner to be described more fully hereinafter. The decoder 136 outputs over line 138 the _^clock pulses 140 (Fig. 9c) and the clock pulses 142 (Fig. 9d) over line 144 in response to receiving the clock pulses 134 over line 118 and the clock pulses 130 over line 132. The decoder 136 is disabled upon receiving a control pulse over line 146 from the gate 128 as a result of the active low blanking pulse transmitted over line 126 from the flip-flop 120 and a display clear signal trans¬ mitted from the generator 112 (Fig. 4) over lines llOd, 148 and through an inverter 150 to one input of the gate 128.

The clock pulses 140 and 142 (Fig. 9) outputted by the decoder 136 are inputted to a NAND gate 152 (Fig. 5B) which outputs the segment drive (SEG DRV) and voltage drive (VDR) pulses 153 (Fig. 9g) over lines 154 and line 156 respectively. The SEG DRV pulse 153 is pulled up to a 12 volt level by the 74LS35 voltage converter or buffer 158 (Fig. 5B) . As will be described more fully hereinafter, the signals VDR are used to control the operation of the transformer 80 (Fig. 4). The pulse 142 (Fig. 9d) appearing on the output line 144 of the decoder 136 (Fig. 5A) and transmitted over line 160 as the column drive signal (COL DRV) 162 (Fig. 9e) are inputted into one input of a plurality of NOR gates 164 whose other input is connected over line 166 to the output of the decoder 124. Column select data signals- appearing on lines HOa-llOc inclusive and transmitted from the data generator 112 (Fig. 4) select which of the column electrodes 28 (Fig. 3) in the panel 92 (Fig. 4) are to be energized. The column select signals are inputted into the decoder 124 (Fig. 5B) which outputs an active low control pulse over one of the output lines 166 in accordance with the column select data signals received in a manner that is well-known in the art. The active low control pulse appearing on the output line 166 is inverted by the corresponding NOR gate 164 and transmitted over line 168 to the base electrode 76 of the NPN transistor 52 (Figs. 3 and 5G)-. The collector electrode 50 of each of the transistors 52 is connected over line 176 to one of the column electrodes 28 (Fig. 3) in the panel 92 (Fig. 4) while the emitter electrode 62 is connected over line 180 to ground through the voltage control diodes 182. The line 176 is connected at point 184 (Figs. 4 and 5c) to a 170 volt DC voltage source over line 94 (Fig. 4) through isolation diode 190, thereby clamping the point 184 at 170 volts. The point 184 is also connected to a 170 volt AC voltage source over line 88 over which the 170 volt AC pull-up drive pulses 186 (Fig. 9f) are transmitted through the diode 188 (Fig. 5C) to charge each of the column elec¬ trodes in the display panel 92 (Fig. 4) to 170 volts. As will be described more fully hereinafter, energizing of one of the transistors 52 (Figs. 4 and 5C) by the signals appearing on line 168 (Fig. 5B and 5C) will ground the selected column electrode enabling the selec¬ ted cells 32a-32g (Fig. 2) connected to the grounded column electrode to be fired. Included in the circuits of Figs. 5B and 5C are line terminators generally indi¬ cated by the numeral 192 which reduces the effect of noise in the circuits.

Referring now to Figs. 7A and 7B arranged in the manner shown in Fig. 8, there is shown a circuit for controlling the operation of the transformer 80 (Fig.

4). Included in the circuit is a transmission line 194 (Fig. 7A) over which is transmitted a DC voltage from the system power supply 84 (Fig. 4) having a voltage level of 28 volts, which voltage is transmitted through an M317 voltage regulator 196 and over line 198 to the primary winding 82 of the transformer 80. The trans¬ former may be an auto-transformer of the type commer¬ cially available from the Coil Craft Company of Cary, Illinois, as part no. B8690. In a manner that is well- known in the art, the current will flow through the primary windings 82 generating a magnetic flux ,around a ferrite core 81 and to the secondary windings 86 which is tapped over line 200 to the drain electrode 202 of a FET transistor indicated generally by the numeral 204 and which is commercially available from Siliconics

Corporation of Santa Barbara, California, as part no. VN88AF. The source electrode 206 of transistor 204 is grounded through lines 208 and 210 while the base elec¬ trode 212 is connected through a LS7435 voltage con¬ verter 214 to line 154 (Fig. 5B and 7B) over which appears the voltage drive signal VDR 153 (Fig. 9g). The transformer 80 is also tapped over line 94 over which is generated by transformer operation a series of voltage pulses having a level of 170 volts AC. The pulses are transmitted through the diode 90 and over line 88 to the column conductors 176 (Fig. 5C) for charging the column electrodes 28 (Fig. 3) to a voltage level of 170 volts. The transformer 80 is center tapped over line 100 and diodes 102, 104 to provide a voltage level of 85 volts DC. This DC voltage level is trans¬ mitted to the segment electrodes 26 (Fig. 3) in a manner to be described more fully hereinafter. The zener diode 104 is used to set the operating voltage of the display 92 (Fig. 4) in a manner that is well-known in the art. The 170 volt AC voltage pulses appearing on line 94 are transmitted through diodes 96 and 98 to clamp the point 184 (Fig. 5C) at 170 volts in the manner described previously. Included in the circuit of Fig. 7B are filter capacitors 97 and 103 for generating the DC voltage by removing the ripple in the AC pulses appearing on lines 94 and 100 together with the load resistor 218. In order to provide a uniform voltage level of the pulses applied to the column electrodes 28 (Fig. 3) and the segment electrodes 26 as the load on the power supply 84 (Fig. 4) varies, a voltage regulator circuit is employed to regulate the 28 volts DC voltage supply 84 (Fig. 4), which circuit includes an NPN 2N3904 trans¬ istor 220 (Fig. 7A) whose base electrode 222 is. connected over line 224 to a voltage divider circuit, comprising the load resistors 216, 226 and 217 (Fig. 7B) which outputs a feedback signal VF whose voltage level is proportional to the voltage level appearing on the secondary windings 86 of the transformer 80 and which is compared with a reference voltage level appearing at the cathode of the zener diode 227 (Fig. 7A) . As the load on the power supply 84 (Fig. 4) varies due to the change in the nui er of cells being fired, the feedback signal VF will exceed the reference ^"voltage turning on the transistor 220 which varies the current level in the regulator 196 resulting in a variation of the voltage level of the pulse being applied to the primary windings 82 of the transformer 80. Thus, when the voltage level in the secondary windings 86 of the transformer 80 becomes too high, the input voltage level applied to the primary windings 82 is reduced.

There is also included in Figs. 7A and 7B an over-current protection circuit for the FET transistor 204 (Fig. 7B), which circuit includes an NPN 2N3904 transistor 228 (Fig. 7A) whose base electrode 230 is connected over lines 232 and 208 to the source electrode 206 of the transistor 204. Upon the current flow in the transistor 204 reaching a predetermined level, the voltage drop across the resistor 234 (Fig. 7B) will allow the transistor 228 to conduct, thereby grounding the regulator 196 and disabling the DC voltage supply to the primary winding 82 of the transformer 80.

The segment select signals SCD are transmitted from the data generator 112 (Fig. 4) over lines llOg (Fig. 7A) and through the voltage converter 236 which raises the voltage level of the signals to 12 volts. In a similar manner, the data clock signals SCC appearing on line llOh (Fig. 7A) and transmitted from the data generator 112 (Fig. 4) are raised to a 12 volt signal level by the 75701 converters 238 and 240 which signals, together with the segment select signals SCD, are trans¬ mitted to the driver circuits 68 and 7Ϊ - (Ej.g. 3) for enabling the selected segments to be fired. The oscil¬ lator circuit generally indicated by the numeral 135 in Fig. 10 includes three 7407 inverters 242, 244 and 246 which, together with the values of the RC circuits shown, will output over line 118 clock pulses having a frequency of 85 KHz. in a manner that is well-known in the art.

In the operation of the gas discharge display panel 92 (Fig. 4), a plurality of binary signals repre- senting a column electrode to be energized will be transmitted over lines HOa-llOc inclusive (Fig. 5A) to the decoder 124 (Fig. 5B) which has been enabled by a blanking pulse appearing on the output line 122 of the flip-flop 120 (Fig. 5A) . Prior to this, the decoder 136 (Fig. 5A) , in response to receiving the clock pulses 130 (Fig. 9b) over line 132 from the flip-flop 120 and the 85 KHz. clock pulses 134 (Fig. 9a) transmitted over line 118, will output the column drive pulses 162 (Fig. 9e) over line 160 to the NOR gates 164 (Fig. 5B) and to the NAND gate 152 which outputs the segment drive and VDR pulses 153 (Fig. 9g) . The VDR pulses 153 are transmitted to the FET transistor 204 (Fig. 7B) which, upon the occurrence of the rising edge of the pulse 153, will forward bias the transistor 204 enabling the transistor to conduct, ^'thereby grounding the primary windings 82 of the transformer 80 and allowing the regulated voltage appearing on line 198 to flow through the primary wind¬ ings 82. Upon the trailing edge of the pulse 153 re¬ turning to zero, the transistor 204 is reversed biased disabling the transistor and removing the ground from the primary windings 82 of the transformer. When this occurs, the flux built up in the ferrite core 81 of the transformer 80 will collapse across the secondary wind¬ ings 86 resulting in 170 volts AC signals appearing in line 94 which are rectified by the diode 96 to produce the pull-up drive pulses 186 (Fig. 9f). These .pulses are transmitted over lines 88 and 176 (Fi . 5C) to the column electrodes 28 (Fig. 3) charging the electrodes to 170 volts DC. During this operation, the segment drive pulses 153 (Fig. 9g) which are 180 degrees out of phase with the pull-up drive pulses 186 (Fig. 9f) are trans¬ mitted to the transistors 44 (Fig. 3) whose operation grounds the segments 32 and allows the column electrodes 28 (Fig. 3) to be charged to 170 volts DC.

After the column electrodes 28 have been charged to 170 volts DC, the column drive pulses 162 (Fig. 9e) enable the NOR gates 164 (Fig. 5B) to output an active high column select signal which had appeared as an active low signal on one of the output lines 166 of the decoder 124 (Fig. 5B). This active high signal which occurs when the pulse 162 goes low is transmitted to the base electrode of one of the transistors 52 (Fig. 5C) enabling the transistor 52 to ground the selected column electrodes over lines 176 and 180 and removing the 170 volt charge on the selected electrodes. Due to the capacitive construction of the cell 20 (Fig. 1), the 170 volts on the grounded column electrodes will remain. At this time, the segment drive pulse 153 (Fig. 9g) will go high enabling the transistors 40 (Fig. 3) associated with the segments 32a-32g (Fig. 2) selected to be fired by the segment select signals appearing on lines llϋg (Fig. 7A) to be operated resulting in the 85 volts

DC appearing on line 108 (Fig. 4) to charge the selected segments to a voltage level of 85 volts. This voltage level combined with the 170 volts appearing on the selected column electrodes results in the firing of the selected segments 32a-32g having a total voltage drop across the segment cell 20 of 255 volts. Those segments which were not selected remain at ground. Upon the column drive pulse 162 (Fig. 9e) returning to a high level, the high pulse being applied to the selected transistors 52 (Fig. 5C) is removed allowing the voltage level of the column electrode to float until the VDR pulse 153 (Fig. 9g) goes high initiating another opera¬ tion of the transformer 80. The use of the flyback op¬ eration of the transformer 80 at the high frequency rate of the system oscillator provides the required volt¬ age drive levels to both the column and segment elec- trodes at a relatively low cost.

Claims

C AIMS :

1. A drive circuit for driving a gas-dis¬ charge device having an array of capacitively-coupled cells in which each cell has a column electrode (28) and a segment electrode (26), said column electrodes (28) being connected by a plurality of column conductors (88) and said segment electrodes (28) being connected by a plurality of segment conductors, including a transformer (80) having primary winding means (82) and secondary winding means (86), characterized in that said secondary winding means (86) is arranged during first time inter¬ vals to supply to said column conductors (88) a first potential, while a reference potential is applied to said segment conductors, said secondary winding means (86) being further arranged during second time intervals occurring alternately with said first time intervals, to supply to selected segment conductors a second potential, said reference potential being applied to selected column conductors, whereby cells at the intersection of selected column and segment conductors are repeatedly ignited.

2. A drive circuit according to claim 1, characterized in that said first and second potentials are each less than the ignition voltage required to ig¬ nite said cells.

3. A drive circuit according to claim 2, characterized in that said primary winding means (82) are coupled to a voltage source (84) and to a switching device (204) adapted to be supplied with clock ..pulses.

4. A drive circuit according to claim 3, characterized in that said switching device includes a field effect transistor (204) having a source-to-drain path coupled in series with said primary winding means (82) and a control electrode arranged to receive said clock pulses.

5. A drive circuit according to claim 4, characterized by first switching means (52) coupled to said column conductors and adapted to apply said refer¬ ence potential thereto in accordance with column select signals applied to said first switching means (52).

6. A drive circuit according to claim 5, characterized by second switching means (40) coupled to said segment conductors and adapted to apply said second potential thereto in accordance with segment select signals applied to said second switching means (40).

7. A drive circuit according to claim 6, characterized by first coupling means (90) connected between said secondary winding means (86) and said column conductors (88) and adapted to apply voltage pulses to said column conductors (88) thereby providing said first potential, and second coupling means (100, 102, 103, 104) coupled between said secondary winding means (86) and said second switching means (40) and adapted to provide thereto a potential level having the value of said second potential.

8. A drive circuit according to claim 7, characterized by third coupling means (97, 98, 100, 102, 190) coupled between said secondary winding means (86) and said column conductors (88) and adapted to clamp said column conductors (88) to said first potential.

9. A drive circuit according to claim 8, characterized by voltage regulating means (196, 220, 226) coupled to said secondary winding means (86) and to said voltage source (84) and adapted to control the voltage level supplied to said primary winding means (82) in accordance with the voltage level developed in said secondary winding means (86).

10. A drive circuit according to claim 9, characterized by over-current protection means (228) coupled between said source-to-drain path of said field effect transistor (204) and said voltage regulating means (196, 220, 226), the arrangement being such that upon the current flow through said source-to-drain path ex¬ ceeding a predetermined level said voltage regulating means (196, 220, 226) is rendered effective to interrupt the voltage supplied to said primary winding means (82) by said voltage source (84).

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