WO1984003997A1 - Self-aligned ldmos and method - Google Patents

Self-aligned ldmos and method Download PDF

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Publication number
WO1984003997A1
WO1984003997A1 PCT/US1984/000171 US8400171W WO8403997A1 WO 1984003997 A1 WO1984003997 A1 WO 1984003997A1 US 8400171 W US8400171 W US 8400171W WO 8403997 A1 WO8403997 A1 WO 8403997A1
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region
forming
impurity type
dmos
area
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Antonio R Alvarez
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Motorola Solutions Inc
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Motorola Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Definitions

  • the present invention relates, in general, to the field of double diffused MOS (DMOS) transistors and to integrated circuits utilizing the same. More particularly, a lateral DMOS (LDMOS) device in accordance with the present invention exhibits an inherently self-aligned channel region allowing for the integration of LDMOS devices having a relatively shorter channel length and, hence, higher gain and superior control than previously described devices. Concomitan ly, the shorter channel length employed provides for the integration of smaller devices and, therefore, a greater number of even faster devices for a given die area.
  • the method of the present invention is fully compatible with standard bipolar processing sequences and eliminates concern over alignment tolerances while simplifying the gate photostep.
  • OMPI dopant concentration profile and the concentration profile of the subsequent N type dopant which forms the NPN emitter concurrently with the formation of the DMOS source and drain.
  • the bulk channel diffusion for the DMOS well is performed followed by the NPN base diffusion, during which minimal oxide is grown in order to mask all P type diffusions from subsequent N type deposition.
  • the patterning of the oxide is carried out in two stages by first selectively opening oxide windows for all N type diffusions with oxide thicker than base oxide, followed by the selective opening of windows for the vertical NPN emitter and DMOS source. In patterning the DMOS source, oxide is removed over the bulk channel diffusion between the source and drift region as well as overlapping into the drift region.
  • the oxide is partially removed over the lateral bulk channel diffusion and part of the drift region, but remains thick enough to mask these regions from the subsequent DMOS source diffusion.
  • the DMOS channel length is determined by the difference between the emitter diffusion and the P-well diffusion, since the oxide window later opened for the DMOS source diffusion or implantation .is essentially the same window initially opened for the P-well formation.
  • DMOS devices fabricated in accordance with this process exhibit a gain constant of approximately 1300, however, still higher gain constants are nonetheless highly desirable.
  • a method and an integrated circuit produced thereby which includes a self-aligned DMOS device having a desired channel length formed by a process comprising the steps of providing a semiconductor substrate of a first impurity type, the substrate presenting a major surface thereof. Thereafter, forming a layer of a second impurity type opposite to the first impurity type on the substrate major surface. Firstly disposing to a first predetermined depth within the layer a region of the first impurity type, the region forming a DMOS well and the first impurity type having a first diffusion rate.
  • an integrated circuit including a self-aligned DMOS device within a semiconductor layer of a given impurity type may be formed by a method comprising the steps of forming an insulating layer overlying the semiconductor layer and removing a predetermined portion of the insulating layer forming an aperture therein.
  • FIG. 1A is a simplified cross sectional view of a portion of an integrated circuit to be fabricated in accordance with the present invention and illustrating the initial stage in the formation of a DMOS P-well through an oxide window by, for example, implantation of boron;
  • FIG. IB is a simplified cross sectional view of that portion of the integrated circuit of FIG. 1A illustrating the initial stage in the formation of a pair of DMOS source regions by, for example, implantation of arsenic through the P-well oxide window of FIG. 1A having a portion thereof previously masked by a photoresist layer?
  • FIG. 1C is a simplified cross sectional view of that portion of the integrated circuit of FIGs. 1A and IB illustrating a completed pair of DMOS devices after subsequent driving in of the P-well and source regions to set the device channel lengths and further illustrating the contact bias and overlying metalizations; and
  • FIG. 2 is a graphic illustration of the gain constant [( V GS ⁇ v ⁇ ) : V ⁇ Dsl achievable in a device in accordance with the present invention in comparison to certain prior art devices not having the desired short channel characteristics attendant those fabricated as herein disclosed.
  • fabrication of a self-aligned LDMOS device in accordance with the present invention begins with the utilization of a substrate 12, which in the embodiment hereinafter described comprises P-semiconductor material. Upon a major surface of substrate 12 is thereafter grown an epitaxial layer 14. Epitaxial layer 14 comprises N-semiconductor material. Thereafter, in a conventional manner, an oxide window 20 is formed on epitaxial layer 14 by patterning of an oxide 18. Oxide window 20 may be formed by any conventional process and is utilized in the forming of P-well 16.
  • P-well 16 is formed by implantation of boron through oxide window 20.
  • a pre-implant oxide of approximately 1,000 angstroms (1000 A) may be formed within oxide window 20 prior to the boron implantation.
  • P-well 16 is formed by implantation at 70 keV resulting in a P-well 16 region of approximately 2200 angstroms (2200 it) .
  • P-well 16 will thereafter partially extend underneath oxide 18 adjacent the periphery of oxide window 20. At this time, it may also be necessary to perform an anneal and drive-in of the silicon surface as a result of the boron implantation step.
  • photoresist 22 is patterned such that a source mask 24 is disposed within oxide window 20 and overlies P-well 16. That portion of photoresist 22 not within oxide window 20 is shown merely as forming the basis for attachment of source mask 24, as oxide 18 alone can mask 24 will mask against the subsequent arsenic implant.
  • arsenic is implanted through the same oxide window 20 depicted in FIG. 1A such that source implant 26 is formed within P-well 16.
  • this implant will be done at 100 keV such that an initial channel length Lj_ is set.
  • Channel length L ⁇ is then presently the distance between source implant 26 and the current edge of P—well 16.
  • channel length j_ will be somewhat less than the desired channel length ultimately formed in the self-aligned LDMOS device of the present invention.
  • FIG. 1C a self-aligned LDMOS structure 10 in accordance with the present invention is shown. That portion of the integrated circuit illus ⁇ trated in FIG. 1C illustrates a simplified construction of a pair of LDMOS devices in the region previously disclosed in FIGs. 1A and IB.
  • the self-aligned LDMOS structure 10 of FIG. 1C follows in processing sequence that portion of the integrated circuit illustrated in FIG. IB subsequent to a removal of photoresist 22 including source mask 24 and an annealing drive-in, and possible oxidation of the implant of P-well 16 and source implant 26.
  • the channel length of self-aligned LDMOS structure 10 is determined. In FIG. 1C, this channel length is illustrated as Lf. As arsenic is a heavier ion than boron, the boron will diffuse more rapidly than arsenic during a subsequent drive-in step. Thus, by driving in both P-well 16 and source implant 26, the channel length of a self-aligned LDMOS structure 10 will increase from ⁇ - of FIG. IB to Lf of FIG. 1C. Thus, the difference in the coefficient of diffusion of the two materials sets the device channel length. By controlling the length of the drive-in time of the implants a consistently reproducible and small channel length Lf may be obtained.
  • drain 28 which may be formed in a conventional manner according to standard bipolar processing sequences.
  • a plurality of isolation regions 30 isolate self-aligned LDMOS structure 10 from adjacent devices.
  • a source contact 32 may be formed within source implant 26 to establish contact to source electrode 40.
  • P-well contact 34 provides contact between P-well 16 and P-well electrode 44.
  • a thin gate oxide 46 overlies the DMOS channel for the provision of gate electrode 38. Gate oxide 46 is typically thermally
  • OMPI grown and provides a clean, highly stable insulation for device operation.
  • Insulating layer 36 serves to isolate source electrode 40, drain electrode 42 and P-well electrode 44.
  • FIG. 2 a comparison between a prior art LDMOS device and a self-aligned LDMOS device in accordance with the present invention is shown.
  • the gain constant for these respective devices is plotted as [(VQ S - V ⁇ ) : .
  • a plot for a prior art LDMOS device having a gain constant of approximately 524 is shown as compared to the self-aligned device of the present invention exhibiting a gain constant of approximately 1618.
  • the self-aligned LDMOS structure 10 of the present invention is process compatible with standard linear processing and produces a high gain LDMOS device that is relatively impervious to photolithographic process variations.
  • the resultant device is faster than the prior art non-self-aligned LDMOS devices as parasitic gate-source capacitance is reduced, while gain is concomitantly increased. Since the gain is greater, for a given gain level, the gate oxide overlying the device channel area can be reduced. This reduction in the gate oxide area translates into higher yields because gate oxide defects have been found to be a major yield limiter in MOS processing.
  • a ⁇ 3:1 increase in gain has been achieved utilizing the self-aligned process herein disclosed. This results in a factor of three reduction in gate oxide area. Assuming Poisson yield statistics, a corresponding 10% increase in yield can be expected due to this reduction in gate oxide defects.
  • the present invention provides for a shorter channel device resulting in an overall smaller structure exhibiting increased device speed.
  • the self- aligned LDMOS device and method of the present invention produces a higher gain constant with a concomitant lower "ON" resistance and further eliminates concern for alignment tolerances while resulting in improved process reproducibility.
  • the device and method of the present invention requires an extra photostep and implant. However, the advantages attendant this extra processing step far outweigh any disadvantages attendant its utilization.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A self-aligned LDMOS device and method and an integrated circuit made thereby which exhibits an inherently by self-aligned channel region allowing for the integration of LDMOS devices having a relatively short channel length (Lf) and hence higher gain than previously described devices. The channel length (Lf) of the device is set by the difference in the coefficient of diffusion between the P-well (16) and source implant (26). The source implant (26) is made through the same oxide window (20) used in forming the P-well (16). The resulting shorter channel length (Lf) provides for the integration of smaller and, therefore, a greater number of even faster devices per given die area. The method of the present invention is fully compatible with standard bipolar processing sequences and eliminates concern over alignment tolerances while simplifying the gate photo step.

Description

SELF-ALIGNED LDMOS AND METHOD
Background of the Invention
The present invention relates, in general, to the field of double diffused MOS (DMOS) transistors and to integrated circuits utilizing the same. More particularly, a lateral DMOS (LDMOS) device in accordance with the present invention exhibits an inherently self-aligned channel region allowing for the integration of LDMOS devices having a relatively shorter channel length and, hence, higher gain and superior control than previously described devices. Concomitan ly, the shorter channel length employed provides for the integration of smaller devices and, therefore, a greater number of even faster devices for a given die area. The method of the present invention is fully compatible with standard bipolar processing sequences and eliminates concern over alignment tolerances while simplifying the gate photostep. To achieve the foregoing benefits of short channel DMOS, attempts to maximize gain in DMOS devices have, in the past, sought to minimize the device channel lengths. Devices constructed in accordance with the various prior art techniques previously utilized have exhibited gain constants [(VQS ~ Vτ) : ^IDS] of little more than 500.
In an attempt to improve this gain factor while at the same time improving the aforementioned parameters as to device size, speed, yield etc. a "self-alignment" process for defining DMOS channel length has been utilized as described in U.S. Patent Number 4,325,180 filed February
15, 1979 and issuing to Curran on April 20, 1982. In this bipolar/DMOS compatible process, an unmasked oxide wash is utilized to define the DMOS channel length. As described, the surface dopant concentration resulting from the DMOS well formation is controlled such that the DMOS threshold voltage is determined by the intersection of the P-well
OMPI dopant concentration profile and the concentration profile of the subsequent N type dopant which forms the NPN emitter, concurrently with the formation of the DMOS source and drain. The bulk channel diffusion for the DMOS well is performed followed by the NPN base diffusion, during which minimal oxide is grown in order to mask all P type diffusions from subsequent N type deposition. After the base diffusion, the patterning of the oxide is carried out in two stages by first selectively opening oxide windows for all N type diffusions with oxide thicker than base oxide, followed by the selective opening of windows for the vertical NPN emitter and DMOS source. In patterning the DMOS source, oxide is removed over the bulk channel diffusion between the source and drift region as well as overlapping into the drift region. During this oxide removal, only that amount of oxide sufficient to expose the bulk channel region is removed. Therefore, the oxide will be fully removed only where the original bulk oxide was removed and thereafter minimally regrown. The oxide is partially removed over the lateral bulk channel diffusion and part of the drift region, but remains thick enough to mask these regions from the subsequent DMOS source diffusion. Thus, the DMOS channel length is determined by the difference between the emitter diffusion and the P-well diffusion, since the oxide window later opened for the DMOS source diffusion or implantation .is essentially the same window initially opened for the P-well formation. DMOS devices fabricated in accordance with this process exhibit a gain constant of approximately 1300, however, still higher gain constants are nonetheless highly desirable.
It is therefore an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof.
It is further an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof which provides for a reduction in parasitic gate-source capacitance.
It is still further an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof which produces a shorter channel device resulting in an overall smaller structure exhibiting increased device speed.
It is still further an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof which allows a reduction in gate oxide area resulting in higher device yield due to decreased gate oxide defects.
It is still further an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof which produces a higher gain constant with a concomitant lower "ON" resistance.
It is still further an object of the present invention to provide an improved self-aligned LDMOS and method for the fabrication thereof which eliminates concern for alignment.^tolerances while resulting in an improved process reproducibilit .
Summary of the Invention
The foregoing and other objects are achieved in the present invention wherein there is provided a method and an integrated circuit produced thereby which includes a self-aligned DMOS device having a desired channel length formed by a process comprising the steps of providing a semiconductor substrate of a first impurity type, the substrate presenting a major surface thereof. Thereafter, forming a layer of a second impurity type opposite to the first impurity type on the substrate major surface. Firstly disposing to a first predetermined depth within the layer a region of the first impurity type, the region forming a DMOS well and the first impurity type having a first diffusion rate. Secondly disposing to a second predetermined depth within the region an area of the second impurity type but at a greater impurity concentration than the layer, the area forming a DMOS source and the second impurity type having a second diffusion rate. Finally, driving in the region and the area for a predetermined length of time whereby the desired channel length is set by the difference between the first and second diffusion rates over the predetermined length of time. In accordance with the method of the present invention an integrated circuit including a self-aligned DMOS device within a semiconductor layer of a given impurity type may be formed by a method comprising the steps of forming an insulating layer overlying the semiconductor layer and removing a predetermined portion of the insulating layer forming an aperture therein. Firstly disposing through the aperture to a predetermined depth within the semiconductor layer a region of an impurity type opposite to the semiconductor layer, the region forming a DMOS well. Masking a portion of the region within the aperture and secondly disposing to a second predetermined depth within an unmasked portion of the region an area of the given impurity type but at a greater impurity concentration than the semiconductor layer, the area forming a DMOS source. Finally, driving in the region and the area for a predetermined length of time whereby the channel length of the DMOS device is set by the difference between the diffusion rates of the region and the area over the predetermined length of time.
Brief Description of the Drawings
The above-mentioned and other features and objects of the invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, wherein:
FIG. 1A is a simplified cross sectional view of a portion of an integrated circuit to be fabricated in accordance with the present invention and illustrating the initial stage in the formation of a DMOS P-well through an oxide window by, for example, implantation of boron;
FIG. IB is a simplified cross sectional view of that portion of the integrated circuit of FIG. 1A illustrating the initial stage in the formation of a pair of DMOS source regions by, for example, implantation of arsenic through the P-well oxide window of FIG. 1A having a portion thereof previously masked by a photoresist layer?
FIG. 1C is a simplified cross sectional view of that portion of the integrated circuit of FIGs. 1A and IB illustrating a completed pair of DMOS devices after subsequent driving in of the P-well and source regions to set the device channel lengths and further illustrating the contact bias and overlying metalizations; and FIG. 2 is a graphic illustration of the gain constant [(VGS ~ vτ) : V^Dsl achievable in a device in accordance with the present invention in comparison to certain prior art devices not having the desired short channel characteristics attendant those fabricated as herein disclosed.
Description of a Preferred Embodiment
Referring now to FIG. 1A, fabrication of a self-aligned LDMOS device in accordance with the present invention begins with the utilization of a substrate 12, which in the embodiment hereinafter described comprises P-semiconductor material. Upon a major surface of substrate 12 is thereafter grown an epitaxial layer 14. Epitaxial layer 14 comprises N-semiconductor material. Thereafter, in a conventional manner, an oxide window 20 is formed on epitaxial layer 14 by patterning of an oxide 18. Oxide window 20 may be formed by any conventional process and is utilized in the forming of P-well 16.
In the embodiment illustrated, P-well 16 is formed by implantation of boron through oxide window 20. Although not illustrated, a pre-implant oxide of approximately 1,000 angstroms (1000 A) may be formed within oxide window 20 prior to the boron implantation. Thereafter, P-well 16 is formed by implantation at 70 keV resulting in a P-well 16 region of approximately 2200 angstroms (2200 it) . As illustrated, P-well 16 will thereafter partially extend underneath oxide 18 adjacent the periphery of oxide window 20. At this time, it may also be necessary to perform an anneal and drive-in of the silicon surface as a result of the boron implantation step.
Referring additionally now to FIG. IB, that portion of the integrated circuit illustrated in FIG. 1A is shown subsequent to a conventional photoresist 22 spin and patterning step. As shown, photoresist 22 is patterned such that a source mask 24 is disposed within oxide window 20 and overlies P-well 16. That portion of photoresist 22 not within oxide window 20 is shown merely as forming the basis for attachment of source mask 24, as oxide 18 alone can mask 24 will mask against the subsequent arsenic implant.
At this point, arsenic is implanted through the same oxide window 20 depicted in FIG. 1A such that source implant 26 is formed within P-well 16. Typically, this implant will be done at 100 keV such that an initial channel length Lj_ is set. Channel length L^, as shown, is then presently the distance between source implant 26 and the current edge of P—well 16. In accordance with the embodiment disclosed, channel length j_ will be somewhat less than the desired channel length ultimately formed in the self-aligned LDMOS device of the present invention.
Referring additionally now to FIG. 1C, a self-aligned LDMOS structure 10 in accordance with the present invention is shown. That portion of the integrated circuit illus¬ trated in FIG. 1C illustrates a simplified construction of a pair of LDMOS devices in the region previously disclosed in FIGs. 1A and IB. The self-aligned LDMOS structure 10 of FIG. 1C follows in processing sequence that portion of the integrated circuit illustrated in FIG. IB subsequent to a removal of photoresist 22 including source mask 24 and an annealing drive-in, and possible oxidation of the implant of P-well 16 and source implant 26.
At this point in the processing sequence, the channel length of self-aligned LDMOS structure 10 is determined. In FIG. 1C, this channel length is illustrated as Lf. As arsenic is a heavier ion than boron, the boron will diffuse more rapidly than arsenic during a subsequent drive-in step. Thus, by driving in both P-well 16 and source implant 26, the channel length of a self-aligned LDMOS structure 10 will increase from ^- of FIG. IB to Lf of FIG. 1C. Thus, the difference in the coefficient of diffusion of the two materials sets the device channel length. By controlling the length of the drive-in time of the implants a consistently reproducible and small channel length Lf may be obtained.
Also illustrated in FIG. 1C is drain 28, which may be formed in a conventional manner according to standard bipolar processing sequences. A plurality of isolation regions 30 isolate self-aligned LDMOS structure 10 from adjacent devices. In like manner, a source contact 32 may be formed within source implant 26 to establish contact to source electrode 40. Likewise, P-well contact 34 provides contact between P-well 16 and P-well electrode 44. A thin gate oxide 46 overlies the DMOS channel for the provision of gate electrode 38. Gate oxide 46 is typically thermally
OMPI grown and provides a clean, highly stable insulation for device operation. Insulating layer 36 serves to isolate source electrode 40, drain electrode 42 and P-well electrode 44. Referring now to FIG. 2, a comparison between a prior art LDMOS device and a self-aligned LDMOS device in accordance with the present invention is shown. In this graphic illustration, the gain constant for these respective devices is plotted as [(VQS - Vτ) :
Figure imgf000010_0001
. A plot for a prior art LDMOS device having a gain constant of approximately 524 is shown as compared to the self-aligned device of the present invention exhibiting a gain constant of approximately 1618.
The self-aligned LDMOS structure 10 of the present invention is process compatible with standard linear processing and produces a high gain LDMOS device that is relatively impervious to photolithographic process variations. The resultant device is faster than the prior art non-self-aligned LDMOS devices as parasitic gate-source capacitance is reduced, while gain is concomitantly increased. Since the gain is greater, for a given gain level, the gate oxide overlying the device channel area can be reduced. This reduction in the gate oxide area translates into higher yields because gate oxide defects have been found to be a major yield limiter in MOS processing. In accordance with the present invention, a ■ 3:1 increase in gain has been achieved utilizing the self-aligned process herein disclosed. This results in a factor of three reduction in gate oxide area. Assuming Poisson yield statistics, a corresponding 10% increase in yield can be expected due to this reduction in gate oxide defects.
What has been provided, therefore, is an improved self-aligned 'LDMOS and method for the fabrication thereof which provides for a reduction in parasitic gate-source capacitance. Further, the present invention provides for a shorter channel device resulting in an overall smaller structure exhibiting increased device speed. The self- aligned LDMOS device and method of the present invention produces a higher gain constant with a concomitant lower "ON" resistance and further eliminates concern for alignment tolerances while resulting in improved process reproducibility. In comparison with prior art techniques, the device and method of the present invention requires an extra photostep and implant. However, the advantages attendant this extra processing step far outweigh any disadvantages attendant its utilization.
While there have been described above the principles of this invention in conjunction with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of the invention. Specifically, other well known processing methods may be utilized in the formation of the LDMOS device well or source region and semiconductor impurity types different from those above-described with respect to the embodiment disclosed may be substituted without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit including a self-aligned DMOS device having a desired channel length formed by a method comprising the steps of: providing a semiconductor substrate of a first impurity type, said substrate presenting a major surface thereof? forming a layer of a second impurity type opposite to said first impurity type on said substrate ajor surf ce? firstly disposing to a first predetermined depth within said layer a region of said first impurity type, said region forming a DMOS well and said first impurity type having a first diffusion rate; secondly disposing to a second predetermined depth within said region an area of said second impurity type but at a greater impurity concentration than said layer, said area forming a DMOS source and said second impurity type having a second diffusion rate? and driving in said region and said area for a predetermined length of time whereby said desired channel length is set by the difference between said first and second diffusion rates over said predetermined length of time.
2. The integrated circuit of claim 1 wherein said steps of providing and forming are carried out by means of P and N type semiconductor material respectively.
3. The integrated circuit of claim 1 wherein said steps of firstly and secondly disposing are carried out by means of implantation of boron and arsenic respectively.
4. A method for forming a self—aligned- DMOS device having a desired channel length comprising the steps of: providing a semiconductor substrate of a first impurity type, said substrate presenting a major surface thereof; forming a layer of a second impurity type opposite to said first impurity type on said substrate major surface; firstly disposing to a first predetermined depth within said layer a region of said first impurity type, said region forming a DMOS well and said first impurity type having a first diffusion rate; secondly disposing to a second predetermined depth within said region an area of said second impurity type but at a greater impurity concentration than said layer, said area forming a DMOS source and said second impurity type having a second diffusion rate; and driving in said region and said area for a predetermined length of time whereby said desired channel length is set by the difference between said first and second diffusion rates over said predetermined length of time,
5. The method of claim 4 wherein said steps of providing and forming are carried out by means of P and N type semiconductor material respectively.
6. An integrated circuit including a self-aligned DMOS device within a semiconductor layer of a given impurity type formed by a method comprising the steps of: forming an insulating layer overlying said semiconductor layer; removing a predetermined portion of said insulating layer forming an aperture therein; firstly disposing through said aperture to a predetermined depth within said semiconductor layer a region of an impurity type opposite to said semiconductor layer, said region forming a DMOS well; asking a portion of said region within said aperture; secondly disposing to a second predetermined depth within an unmasked portion of said region an area of said given impurity type but at a greater impurity concentration than said semiconductor layer, said area forming a DMOS source; and driving in said region and said area for a predetermined length of time whereby the channel length of said DMOS device is set by the difference between the diffusion rates of said region and said area over said predetermined length of time.
7, The integrated circuit of claim 6 wherein said step of- removing is a patterned oxide cut.
8. ' A method for forming a self-aligned DMOS device within a semiconductor layer of a given impurity type comprising the steps of: forming an insulating layer overlying said semiconductor layer; removing a predetermined portion of said insulating layer forming an aperture therein; firstly disposing through said aperture to a predetermined depth within said semiconductor layer a region of an impurity type opposite to said semiconductor layer, said region forming a DMOS well; masking a portion of said region within said aperture; secondly disposing to a second predetermined depth within an unmasked portion of said region an area of said given impurity type but at a greater impurity concentration than said semiconductor layer, said area forming a DMOS source; and
OMPI 'driving in said region and said area for a predetermined length of time whereby the channel length of said DMOS device is set by the difference between the diffusion rates of said region and said area over said predetermined length of time.
9. The method of claim 8 wherein said step of masking is carried out by means of photoresist.
10. The method of claim 8 wherein said steps of firstly and secondly disposing are carried out by means of implantation of boron and arsenic respectively.
PCT/US1984/000171 1983-04-04 1984-02-08 Self-aligned ldmos and method Ceased WO1984003997A1 (en)

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WO1998049732A3 (en) * 1997-04-28 1999-02-04 Koninkl Philips Electronics Nv Lateral mos transistor device
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WO1998049732A3 (en) * 1997-04-28 1999-02-04 Koninkl Philips Electronics Nv Lateral mos transistor device
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