WO1987006766A1 - Multiple integrated circuit interconnection arrangement - Google Patents

Multiple integrated circuit interconnection arrangement Download PDF

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Publication number
WO1987006766A1
WO1987006766A1 PCT/US1987/000938 US8700938W WO8706766A1 WO 1987006766 A1 WO1987006766 A1 WO 1987006766A1 US 8700938 W US8700938 W US 8700938W WO 8706766 A1 WO8706766 A1 WO 8706766A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrical
group
interconnections
film
major surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1987/000938
Other languages
French (fr)
Inventor
Vahram S. Cardashian
Jerald M. Loy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Priority to DE8787903515T priority Critical patent/DE3773384D1/en
Publication of WO1987006766A1 publication Critical patent/WO1987006766A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits

Definitions

  • the present invention relates to the electrical interconnecting of monolithic integrated circuits, and more particularly, to interconnecting monolithic integrated circuits in a preformed interconnection structure of only a small area.
  • Monolithic integrated circuits must be mounted in some mechanically secure manner during use, and must be electrically interconnected with other portions of the electronic system in hich it is to operate. There is a desire to accomplish this in as "" little space as possible and at the lowest cost possible while assuring reliable interconnection during use in a chosen environment.
  • a typical approach is to mount such monolithic integrated circuit chips on a printed circuit board or on a ceramic substrate. Electrical interconnections to the chip electrical terminations are made from conductive tracks provided on the surface of such board or substrate. There are limits, however, to how closely monolithic integrated circuits can be arrayed on printed circuit boards due to limitations in printed circuit board track placement technology. Closer packing is possible on ceramic substrates, but they are relatively expensive.
  • Such a film can have many frames and so many integrated circuits contained therein, one in each frame.
  • the film with such integrated circuits can then be provided to a bonding machine which may automatically index a frame forward for each bonding, cut the tape interconnections near the edge of the film opening, and bond the remaining ends of the tape interconnections to a board or substrate to thereby interconnect the chip in the frame thereto.
  • tape interconnections can be made quite small, some improvement in density can be achieved at least on ceramic substrates.
  • the use of tape carrier feed in an automatic bonding machine can aid in the reduction of cost. However, greater integrated circuit packing densities are desired along with a further reduction in cost.
  • the present invention provides a means for interconnecting a plurality of monolithic integrated circuits through use of a flexible insulating film with electrical interconnections on either side which are themselves interconnected at selected locations through the flexible film.
  • the insulating layer on the side opposite that to which the monolithic integrated circuits are connected is positioned beneath the connection place for such integrated circuits to support the flexible carrier during the interconnection of the integrated circuits.
  • Figure 1 shows an exploded view of a portion of the present invention.
  • FIG. 2 shows an integrated portion of the present invention
  • Figure 3 shows a cross section of a portion of Figure 2.
  • Figure 1 shows an exploded view of levels of a flexible, electrical interconnection means for monolithic integrated circuits and possibly other circuit components. If to be provided as part of a tape, the portion shown would be a * "frame* in such tape. The tape would consist of a repeated number of such frames.
  • a polyimide film 10 which is the flexible electrical insulating material.
  • This film is typically one or two mils in thickness.
  • the portion of such film shown is in the form of a tape, this portion would repeat and these duplicates would extend in an elongated fashion to the right and to the left of the break lines shown.
  • the interconnection means could be provided in the form of a sheet having repeated patterns extending in more than one or two directions.
  • Adhering to a major surface on each side of film 10 are a group of fine conductive interconnection lines or interconnections, a first group, 11, shown above film 10 and a second group, 12, shown below film 10. These are shown with dashed lines around them to suggest there is a layer devoted to each group, but the interconnections are independent from each other within the group with which there is no actual physical conductive contact.
  • each of the interconnections in groups 11 and 12 are formed of copper over chromium with the chromium adhering to film 10.
  • Each interconnection may be as fine as two mils wide with a 5 spacing of again two mils from one another, edge to edge.
  • Such fine interconnection lines and close spacing are provided using common metal deposition and photolithography techniques. For instance, the sputtering of chromium and some copper onto film 10
  • ⁇ - ⁇ can be followed by electroplating the remaining copper to the desired thickness. Then, using photolitho ⁇ graphy methods common in intergrated circuit fabrication, the patterns for each of the interconnections in groups 1-1 and 12 can be defined
  • Selected registration markings may be provided in the same manner, such markings being used to determine relative positions on either side of film 10.
  • selected interconnections in 0 group 11 are electrically interconnected to selected interconnections in group 12 through electrical conductors provided in openings, 15, in film 10. Copper is plated through these openings to provide such through-film interconnections.
  • protective layers are protective layers. The upper one of these protective layers, 16, is over group 11 and on exposed portions of the corresponding major surface of film 10. The lower one of these protective layers, 17, is over group 12 and on exposed portions of the corresponding major surface of film 10.
  • Protective layers 16 and 17 are of flexible electrical insulating material, again typically polyimide.
  • Openings are provided in protective layers 16 and 17 to accommodate providing interconnections to terminations 13, for monolithic integrated circuit chips, and to terminations 14, including those terminations occurring below the interconnections in group 12, for providing interconnections to external circuits.
  • These openings in protective layer 16 are designated 13' and 14' in accordance with the terminations in interconnection group 11.
  • there are some openings provided for external connection through protective layer 17 also designated 14' which correspond to terminations in interconnection group 12.
  • sprocket holes, 18, for sprockets to drive the tape in a machine adapted for use in combining the portion shown in Figure 1 into a next higher assemblage in a manufacturing process are sprocket holes 18, for sprockets to drive the tape in a machine adapted for use in combining the portion shown in Figure 1 into a next higher assemblage in a manufacturing process.
  • Sprocket holes 18 are precisely located with respect to the patterns of interconnections in Figure 1 including those of group 11 and 12, and with the openings for interconnections 15 in film 10.
  • control means driving such sprockets in such a machine can precisely position such a tape along the direction this tape is driven by them.
  • Other circuits on such a board or substrate could then be interconnected to those in the integrated circuit means of Figure 1 by interconnections from terminations 14 to such circuits.
  • a printed circuit board or a ceramic substrate having such interconnection means used thereon would have thereon a considerable increase in circuit component density over that which could be otherwise achieved on such a board, and a decrease in cost over what could be achieved with such a substrate.
  • Figure 2 shows as an integrated item the exploded view portion of Figure 1, with the layers of Figure 1 formed into a full series of interconnection means in abbreviated tape form.
  • Figure 2 indicates monolithic integrated circuits chips, 20, to be mated and interconnected to such an interconnection means with a form suggesting thermocompression bonding of these chips. However, other bonding technologies can be used, such as ultrasonic bonding.
  • the patterns of Figure 1 are then repeated as "frames" along the tape shown in Figure 2 or, if a sheet rather than a tape, repeated across the sheet. Additional protective coatings or structures, including electrically insulating ones, can be provided on or over chips 20 or over other kinds of electrical circuit components mounted on the interconnection means.
  • Figure 3 is a cross section of a portion of Figure 2 at a location that is the place of mounting a monolithic integrated circuit chip, 30, in the interconnection means by thermocompression bonding.
  • Protective layer 17 fully fills in about the interconnections of interconnection group 12 to provide firm support under chip 30 during bonding of the wire interconnection leads, 31, between the chip electrical termination, 32, and interconnections in interconnection group 11.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

A flexible chip interconnection means includes a flexible film (10) having interconnection lines (11, 12) formed on opposite sides thereof, with selected of the interconnection lines from one side connected by through-film conductors (15) to interconnection lines on the other side. Insulating layers (16, 17) cover both sets of lines on the other side. Insulating layers cover both sets of interconnection lines. Multi-chip circuits can be formed on the film with the interconnection lines directly connecting the chips.

Description

MULTIPLE INTEGRATED CIRCUIT INTERCONNECTION ARRANGEMENT
BACKGROUND OF THE INVENTION The present invention relates to the electrical interconnecting of monolithic integrated circuits, and more particularly, to interconnecting monolithic integrated circuits in a preformed interconnection structure of only a small area. Monolithic integrated circuits must be mounted in some mechanically secure manner during use, and must be electrically interconnected with other portions of the electronic system in hich it is to operate. There is a desire to accomplish this in as "" little space as possible and at the lowest cost possible while assuring reliable interconnection during use in a chosen environment. A typical approach is to mount such monolithic integrated circuit chips on a printed circuit board or on a ceramic substrate. Electrical interconnections to the chip electrical terminations are made from conductive tracks provided on the surface of such board or substrate. There are limits, however, to how closely monolithic integrated circuits can be arrayed on printed circuit boards due to limitations in printed circuit board track placement technology. Closer packing is possible on ceramic substrates, but they are relatively expensive.
The density of monolithic integrated circuits across such substrates can often be increased, and the cost of mounting and interconnecting such integrated circuits on substrates and boards can be reduced through the use of chip carrier films. Such films are o_ an electrical insulator material having conductive interconnections provided thereon. In each "frame" along the film, an individual monolithic integrated circuit is connected to the corresponding set of interconnectors therein which radiate into the chip often bridging an opening in the film frame interior over which the chip is provided. That is, the frame interconnections from the edges of the film around the frame opening to chip electrical interconnections, the opening being provided under the ends of the tape interconnections to which the monolithic integrated circuit is interconnected and under the chip itself. Such a film can have many frames and so many integrated circuits contained therein, one in each frame. The film with such integrated circuits can then be provided to a bonding machine which may automatically index a frame forward for each bonding, cut the tape interconnections near the edge of the film opening, and bond the remaining ends of the tape interconnections to a board or substrate to thereby interconnect the chip in the frame thereto.
Because the tape interconnections can be made quite small, some improvement in density can be achieved at least on ceramic substrates. The use of tape carrier feed in an automatic bonding machine can aid in the reduction of cost. However, greater integrated circuit packing densities are desired along with a further reduction in cost.
SUMMARY OP THE INVENTION
The present invention provides a means for interconnecting a plurality of monolithic integrated circuits through use of a flexible insulating film with electrical interconnections on either side which are themselves interconnected at selected locations through the flexible film. There is an insulating layer over each group of interconnections on either side of the flexible film with openings in the layers to permit interconnection of monolithic integrated circuits, other circuit components, or interconnections to external circuits. The insulating layer on the side opposite that to which the monolithic integrated circuits are connected is positioned beneath the connection place for such integrated circuits to support the flexible carrier during the interconnection of the integrated circuits. - .-
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows an exploded view of a portion of the present invention.
Figure 2 shows an integrated portion of the present invention, and
Figure 3 shows a cross section of a portion of Figure 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 shows an exploded view of levels of a flexible, electrical interconnection means for monolithic integrated circuits and possibly other circuit components. If to be provided as part of a tape, the portion shown would be a* "frame* in such tape. The tape would consist of a repeated number of such frames.
At the center or core of the interconnection means is a polyimide film, 10, which is the flexible electrical insulating material. This film is typically one or two mils in thickness. Again, if the portion of such film shown is in the form of a tape, this portion would repeat and these duplicates would extend in an elongated fashion to the right and to the left of the break lines shown. However, though the structure shown in Figure 1, and that in Figure 2 for that matter, suggest the interconnection means in the form of a tape, a form which is very convenient, the interconnection means could be provided in the form of a sheet having repeated patterns extending in more than one or two directions. Adhering to a major surface on each side of film 10 are a group of fine conductive interconnection lines or interconnections, a first group, 11, shown above film 10 and a second group, 12, shown below film 10. These are shown with dashed lines around them to suggest there is a layer devoted to each group, but the interconnections are independent from each other within the group with which there is no actual physical conductive contact.
The interconnections in group 11 are shown drawn all in one direction as they are in group 12 also in an orthogonal direction, but this is a matter of design convenience and is not necessarily the only geometrical pattern which could be used. Group 11 shows an inteconnection pattern in several places, 13, adapted for accepting interconnections of monolithic integrated circuits. Furthermore, group 11 also shows a series of interconnection terminals, 14, along the sides thereof suitable for use in connecting to external circuits. Such external circuit interconnections can also be made by the group 12 interconnections. Typically, each of the interconnections in groups 11 and 12 are formed of copper over chromium with the chromium adhering to film 10. Each interconnection may be as fine as two mils wide with a 5 spacing of again two mils from one another, edge to edge. Such fine interconnection lines and close spacing are provided using common metal deposition and photolithography techniques. For instance, the sputtering of chromium and some copper onto film 10
~-~ can be followed by electroplating the remaining copper to the desired thickness. Then, using photolitho¬ graphy methods common in intergrated circuit fabrication, the patterns for each of the interconnections in groups 1-1 and 12 can be defined
15 and formed. Selected registration markings may be provided in the same manner, such markings being used to determine relative positions on either side of film 10.
In addition, selected interconnections in 0 group 11 are electrically interconnected to selected interconnections in group 12 through electrical conductors provided in openings, 15, in film 10. Copper is plated through these openings to provide such through-film interconnections. 5 Protecting each of interconnection groups 11 and 12, and also electrically insulating these groups from external items, except as desired through openings provided in these layers, are protective layers. The upper one of these protective layers, 16, is over group 11 and on exposed portions of the corresponding major surface of film 10. The lower one of these protective layers, 17, is over group 12 and on exposed portions of the corresponding major surface of film 10. Protective layers 16 and 17 are of flexible electrical insulating material, again typically polyimide. Openings are provided in protective layers 16 and 17 to accommodate providing interconnections to terminations 13, for monolithic integrated circuit chips, and to terminations 14, including those terminations occurring below the interconnections in group 12, for providing interconnections to external circuits. These openings in protective layer 16 are designated 13' and 14' in accordance with the terminations in interconnection group 11. Similarly, there are some openings provided for external connection through protective layer 17 also designated 14' which correspond to terminations in interconnection group 12.
Further shown in Figure 1, for the situation in which the interconnection means portion of Figure 1 is part of a tape, are sprocket holes, 18, for sprockets to drive the tape in a machine adapted for use in combining the portion shown in Figure 1 into a next higher assemblage in a manufacturing process. Sprocket holes 18 are precisely located with respect to the patterns of interconnections in Figure 1 including those of group 11 and 12, and with the openings for interconnections 15 in film 10. Thus, control means driving such sprockets in such a machine can precisely position such a tape along the direction this tape is driven by them. A typical next assembly for such an interconnection means once the monolithic integrated circuit components have been mounted thereon, along with any' other circuit components to be also mounted, would be to provide this interconnection means on a printed wiring board or on a ceramic substrate. Other circuits on such a board or substrate could then be interconnected to those in the integrated circuit means of Figure 1 by interconnections from terminations 14 to such circuits. Because of the very dense packing of monolithic integrated circuits and other circuit components which can be achieved with the interconnection means of Figure 1, a printed circuit board or a ceramic substrate having such interconnection means used thereon would have thereon a considerable increase in circuit component density over that which could be otherwise achieved on such a board, and a decrease in cost over what could be achieved with such a substrate.
Figure 2 shows as an integrated item the exploded view portion of Figure 1, with the layers of Figure 1 formed into a full series of interconnection means in abbreviated tape form. Figure 2 indicates monolithic integrated circuits chips, 20, to be mated and interconnected to such an interconnection means with a form suggesting thermocompression bonding of these chips. However, other bonding technologies can be used, such as ultrasonic bonding. The patterns of Figure 1 are then repeated as "frames" along the tape shown in Figure 2 or, if a sheet rather than a tape, repeated across the sheet. Additional protective coatings or structures, including electrically insulating ones, can be provided on or over chips 20 or over other kinds of electrical circuit components mounted on the interconnection means.•
Figure 3 is a cross section of a portion of Figure 2 at a location that is the place of mounting a monolithic integrated circuit chip, 30, in the interconnection means by thermocompression bonding. Protective layer 17 fully fills in about the interconnections of interconnection group 12 to provide firm support under chip 30 during bonding of the wire interconnection leads, 31, between the chip electrical termination, 32, and interconnections in interconnection group 11.

Claims

Q lύliS. The embodiments of the invention in which an exclusive property or right is claimed are defined as follows:
1. An electrical interconnection means for selected electronic circuit components also usable with selected other circuit components, said interconnection means comprising: a flexible film of an electrical insulating material having a first major surface and a second major surface on opposite sides thereof; a first group of electrical .interconnections of a first pattern, said first group of electrical interconnections adhering to said first major surface and located entirely within a selected first area at least at one site in said flexible film, said first pattern having a plurality of places therein where portions of members of said first group of electrical interconnections are arranged in a predetermined arrangement to thereby be capable of permitting electrical contacts of a selected nature to be made to a correspond- ing selected monolithic integrated circuit chip; a second group of electrical interconnections of a second pattern, said second group of electrical interconnections adhering to said second major surface and located entirely within a selected second area opposite said first area; at least one through-film electrical interconnec¬ tion, located in an opening through said flexible film, said through-film electrical interconnection serving to electrically interconnect at least one member of said first group of electrical interconnections to at least one member of said second group of electrical interconnections; a first protective layer of an electrical insulating material disposed over said first group of electrical interconnections, except at selected interconnection locations including said portions of said members of said first group of electrical interconnec¬ tions in said predetermined arrangement for permitting electrical contacts, and on said first major surface in said first area; and a second protective layer of an electrical insulating material disposed over said second group of electrical interconnections, except at selected contact locations, if any, and on said second major surface within said second area, said second protective layer having its resulting surface opposite that surface thereof against said second major surface and substantially parallel to said second major surface at those said places having said predetermined arrangements of said portions of said first group of electrical interconnections.
2. The apparatus of claim 1 wherein the said one site is an initial site, and said flexible film has a plurality of similar sites at each of which there is substantially a duplicate of said first group of electrical interconnections, said second group of electrical interconnections, said through-film interconnections, said first protective layer, and said second protective layer.
3. The apparatus of claim 1 wherein monolithic integrated circuit chips are electrically interconnected at those said places having said predetermined arrangements of said portions of said first group of electrical interconnections.
4. The apparatus of claim 1 wherein there is a plurality of said through-film electrical interconnections.
5. The apparatus of claim 2 wherein said duplicate sites are formed one after another repeatedly in an array.
6. The apparatus of claim 5 wherein said array is a linear array and part of a tape based on said flexible film, said tape having sprocket openings therein at opposite edges thereof in a fixed relationship with said opening for said through-film electrical interconnection.
PCT/US1987/000938 1986-05-01 1987-04-28 Multiple integrated circuit interconnection arrangement Ceased WO1987006766A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE8787903515T DE3773384D1 (en) 1986-05-01 1987-04-28 CONNECTING ARRANGEMENT FOR MULTIPLE INTEGRATED CIRCUITS.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85900086A 1986-05-01 1986-05-01
US859,000 1986-05-01

Publications (1)

Publication Number Publication Date
WO1987006766A1 true WO1987006766A1 (en) 1987-11-05

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PCT/US1987/000938 Ceased WO1987006766A1 (en) 1986-05-01 1987-04-28 Multiple integrated circuit interconnection arrangement

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US (1) US5126920A (en)
EP (1) EP0305398B1 (en)
JP (1) JPH01503663A (en)
CA (1) CA1311856C (en)
DE (1) DE3773384D1 (en)
WO (1) WO1987006766A1 (en)

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US8754234B2 (en) 2007-11-30 2014-06-17 Bayer Cropscience Ag Chiral 2-(benzylsulfinyl)thiazole derivatives and 2-[(1H-pyrazol-4-ylmethyl)sulfinyl]thiazole derivatives, processes for their preparation and their use as herbicides and plant growth regulators
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Also Published As

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DE3773384D1 (en) 1991-10-31
US5126920A (en) 1992-06-30
EP0305398A1 (en) 1989-03-08
CA1311856C (en) 1992-12-22
JPH01503663A (en) 1989-12-07
EP0305398B1 (en) 1991-09-25

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