WO1989009471A3 - Memory selftest method and apparatus - Google Patents

Memory selftest method and apparatus Download PDF

Info

Publication number
WO1989009471A3
WO1989009471A3 PCT/US1989/001036 US8901036W WO8909471A3 WO 1989009471 A3 WO1989009471 A3 WO 1989009471A3 US 8901036 W US8901036 W US 8901036W WO 8909471 A3 WO8909471 A3 WO 8909471A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
series
data
data words
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1989/001036
Other languages
French (fr)
Other versions
WO1989009471A2 (en
Inventor
Donald C Pierce
Edward H Utzig
Robert N Crouse
Noreen Hession
Donald W Smelser
Hansel A Collins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to EP89905305A priority Critical patent/EP0366757B1/en
Priority to DE68923531T priority patent/DE68923531T2/en
Publication of WO1989009471A2 publication Critical patent/WO1989009471A2/en
Publication of WO1989009471A3 publication Critical patent/WO1989009471A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being the inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.
PCT/US1989/001036 1988-04-01 1989-03-15 Memory selftest method and apparatus Ceased WO1989009471A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP89905305A EP0366757B1 (en) 1988-04-01 1989-03-15 Memory selftest method and apparatus
DE68923531T DE68923531T2 (en) 1988-04-01 1989-03-15 METHOD AND DEVICE FOR THE MEMORY SELF-TEST.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17669988A 1988-04-01 1988-04-01
US176,699 1988-04-01

Publications (2)

Publication Number Publication Date
WO1989009471A2 WO1989009471A2 (en) 1989-10-05
WO1989009471A3 true WO1989009471A3 (en) 1989-11-16

Family

ID=22645472

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1989/001036 Ceased WO1989009471A2 (en) 1988-04-01 1989-03-15 Memory selftest method and apparatus

Country Status (5)

Country Link
EP (1) EP0366757B1 (en)
JP (1) JP2740899B2 (en)
CA (1) CA1304821C (en)
DE (1) DE68923531T2 (en)
WO (1) WO1989009471A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0441088A1 (en) * 1990-01-24 1991-08-14 International Business Machines Corporation Memory card resident diagnostic testing
US5274648A (en) * 1990-01-24 1993-12-28 International Business Machines Corporation Memory card resident diagnostic testing
JP3849884B2 (en) * 1995-06-09 2006-11-22 富士通株式会社 Apparatus for generating a sequence of binary numbers, method for testing for faults in a storage module, and system for testing a storage module
US6477673B1 (en) * 1999-07-30 2002-11-05 Stmicroelectronics, Inc. Structure and method with which to generate data background patterns for testing random-access-memories
DE10135583B4 (en) * 2001-07-20 2004-05-06 Infineon Technologies Ag Data generator for generating test data for word-oriented semiconductor memories
DE102004051346A1 (en) 2004-10-21 2006-05-04 Infineon Technologies Ag Semiconductor device test device, in particular data buffer component with semiconductor device test device, and semiconductor device test method
DE102004051344A1 (en) 2004-10-21 2006-05-04 Infineon Technologies Ag Semiconductor-component test device e.g. for testing integrated computing circuits, uses shift register with additional memory device for tapping further pseudo-random value
CN111044886B (en) * 2019-12-09 2022-05-13 北京时代民芯科技有限公司 A DDR2/3 PHY BIST data channel test vector generation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0031706A2 (en) * 1979-12-27 1981-07-08 Fujitsu Limited Apparatus and method for testing semiconductor memory devices
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831762B2 (en) * 1974-08-21 1983-07-08 横河電機株式会社 Random Shingo Hatsusei Cairo
JPS5199439A (en) * 1975-02-28 1976-09-02 Fujitsu Ltd
JPS54132145A (en) * 1978-04-06 1979-10-13 Nec Corp False random code generator
JPS58101515A (en) * 1981-12-14 1983-06-16 Agency Of Ind Science & Technol Binary random number generator
JPS59166879A (en) * 1983-03-14 1984-09-20 Nec Corp Integrated circuit device
US4715034A (en) * 1985-03-04 1987-12-22 John Fluke Mfg. Co., Inc. Method of and system for fast functional testing of random access memories

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
EP0031706A2 (en) * 1979-12-27 1981-07-08 Fujitsu Limited Apparatus and method for testing semiconductor memory devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Vol. 25, No. 3A, August 1982 (Armonk, NY, US) F. TSUI: "Testing of Memory Parts", pages 1216-1227 *
Proceedings of the 1984 International Test Conference, 16-18 October 1984 Philadelphia, IEEE (US) Z. SUN et al.: "Self-Testing of Embedded RAMs", pages 148-156 *
Proceedings of the 1986 International Test Conference, 8-11 September 1986 Philadelphia, IEEE (US) W. DAEHN et al.: "A Test Generator IC for Testing Large CMOS-RAMs", pages 18-24 *

Also Published As

Publication number Publication date
CA1304821C (en) 1992-07-07
JP2740899B2 (en) 1998-04-15
EP0366757B1 (en) 1995-07-19
EP0366757A1 (en) 1990-05-09
DE68923531T2 (en) 1996-04-04
DE68923531D1 (en) 1995-08-24
WO1989009471A2 (en) 1989-10-05
JPH0277860A (en) 1990-03-16

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